公开(公告)号：US20130075919A1

公开(公告)日：2013-03-28

申请号：US13679792

申请日：2012-11-16

Applicant: STATS ChipPAC, Ltd.

Inventor： JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/50

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/186 ,  H05K3/007 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83

Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.

Abstract translation: Fo-WLCSP具有围绕半导体管芯形成的第一聚合物层。 通过围绕半导体管芯的周边的第一聚合物层形成第一导电通孔。 第一互连结构形成在第一聚合物层的第一表面上并电连接到第一导电通孔。 第一互连结构具有第二聚合物层和穿过第二聚合物层形成的多个第二通孔。 第二互连结构形成在第一聚合物层的第二表面上并电连接到第一导电通孔。 第二互连结构具有第三聚合物层和穿过第三聚合物层形成的多个第三通孔。 可以以PoP布置将半导体封装安装到WLCSP。 半导体封装通过第一互连结构或第二互连结构电连接到WLCSP。

公开(公告)号：US20150228590A1

公开(公告)日：2015-08-13

申请号：US14697950

申请日：2015-04-28

Applicant: STATS ChipPAC, Ltd.

Inventor： JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

IPC: H01L23/552 ,  H01L21/768 ,  H01L23/528 ,  H01L21/52 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L21/52 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.

Abstract translation: 通过在载体上形成散热器来制造半导体器件。 半导体管芯安装在散热器上方，第一表面朝向散热器。 第一绝缘层形成在半导体管芯和散热器上。 在第一绝缘层中形成通孔。 第一导电层形成在第一绝缘层之上，并通过通孔和半导体管芯上的接触焊盘连接到散热器。 散热器从半导体管芯的第一表面延伸到通孔。 在第一导电层上形成第二绝缘层。 第二导电层电连接到第一导电层。 载体被移除。 散热器从半导体管芯散热，并提供屏蔽器件间干扰。 散热器通过第一导电层接地。

公开(公告)号：US09401347B2

公开(公告)日：2016-07-26

申请号：US14600825

申请日：2015-01-20

Applicant: STATS ChipPAC, Ltd.

Inventor： SinJae Lee ,  JinGwan Kim ,  JiHoon Oh ,  JaeHyun Lim ,  KyuWon Lee

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

公开(公告)号：US20150137334A1

公开(公告)日：2015-05-21

申请号：US14600825

申请日：2015-01-20

Applicant: STATS ChipPAC, Ltd.

Inventor： SinJae Lee ,  JinGwan Kim ,  JiHoon Oh ,  JaeHyun Lim ,  KyuWon Lee

IPC: H01L25/065 ,  H01L23/552 ,  H01L21/768 ,  H01L21/56 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

Abstract translation: 半导体器件具有互连结构，其中腔部分地穿过互连结构形成。 第一半导体管芯安装在空腔中。 通过第一半导体管芯形成第一TSV。 在互连结构和第一半导体管芯上沉积粘合剂层。 屏蔽层安装在第一半导体管芯上。 屏蔽层通过粘合剂层固定到第一半导体管芯，并通过第一TSV和互连结构接地以阻止电磁干扰。 第二半导体管芯安装到屏蔽层并电连接到互连结构。 通过第二半导体管芯形成第二TSV。 密封剂沉积在屏蔽层，第二半导体管芯和互连结构之上。 通过屏蔽层形成狭缝以使密封剂流入空腔并覆盖第一半导体管芯。

公开(公告)号：US09379064B2

公开(公告)日：2016-06-28

申请号：US14697950

申请日：2015-04-28

Applicant: STATS ChipPAC, Ltd.

Inventor： JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L21/14 ,  H01L23/10 ,  H01L23/34 ,  H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/538 ,  H01L21/52 ,  H01L21/768 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/52 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.

公开(公告)号：US08937371B2

公开(公告)日：2015-01-20

申请号：US13935312

申请日：2013-07-03

Applicant: STATS ChipPAC, Ltd.

Inventor： SinJae Lee ,  JinGwan Kim ,  JiHoon Oh ,  JaeHyun Lim ,  KyuWon Lee

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

Abstract translation: 半导体器件具有互连结构，其中腔部分地穿过互连结构形成。 第一半导体管芯安装在空腔中。 通过第一半导体管芯形成第一TSV。 在互连结构和第一半导体管芯上沉积粘合剂层。 屏蔽层安装在第一半导体管芯上。 屏蔽层通过粘合剂层固定到第一半导体管芯，并通过第一TSV和互连结构接地以阻止电磁干扰。 第二半导体管芯安装到屏蔽层并电连接到互连结构。 通过第二半导体管芯形成第二TSV。 密封剂沉积在屏蔽层，第二半导体管芯和互连结构之上。 通过屏蔽层形成狭缝以使密封剂流入空腔并覆盖第一半导体管芯。

公开(公告)号：US08836114B2

公开(公告)日：2014-09-16

申请号：US13679792

申请日：2012-11-16

Applicant: STATS ChipPAC, Ltd.

Inventor： JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

IPC: H01L23/52 ,  H05K1/18 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56 ,  H01L21/50 ,  H05K3/46 ,  H01L21/768 ,  H01L25/10 ,  H05K3/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/186 ,  H05K3/007 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83

Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.

Abstract translation: Fo-WLCSP具有围绕半导体管芯形成的第一聚合物层。 通过围绕半导体管芯的周边的第一聚合物层形成第一导电通孔。 第一互连结构形成在第一聚合物层的第一表面上并电连接到第一导电通孔。 第一互连结构具有第二聚合物层和穿过第二聚合物层形成的多个第二通孔。 第二互连结构形成在第一聚合物层的第二表面上并电连接到第一导电通孔。 第二互连结构具有第三聚合物层和穿过第三聚合物层形成的多个第三通孔。 可以以PoP布置将半导体封装安装到WLCSP。 半导体封装通过第一互连结构或第二互连结构电连接到WLCSP。

公开(公告)号：US20130292804A1

公开(公告)日：2013-11-07

申请号：US13935312

申请日：2013-07-03

Applicant: STATS ChipPAC, Ltd.

Inventor： SinJae Lee ,  JinGwan Kim ,  JiHoon Oh ,  JaeHyun Lim ,  KyuWon Lee

IPC: H01L23/552

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

Abstract translation: 半导体器件具有互连结构，其中腔部分地穿过互连结构形成。 第一半导体管芯安装在空腔中。 通过第一半导体管芯形成第一TSV。 在互连结构和第一半导体管芯上沉积粘合剂层。 屏蔽层安装在第一半导体管芯上。 屏蔽层通过粘合剂层固定到第一半导体管芯，并通过第一TSV和互连结构接地以阻止电磁干扰。 第二半导体管芯安装到屏蔽层并电连接到互连结构。 通过第二半导体管芯形成第二TSV。 密封剂沉积在屏蔽层，第二半导体管芯和互连结构之上。 通过屏蔽层形成狭缝以使密封剂流入空腔并覆盖第一半导体管芯。