公开(公告)号：US09589810B2

公开(公告)日：2017-03-07

申请号：US14950200

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Daisuki Taniguchi

IPC: H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L23/544 ,  H01L21/02 ,  H01L29/861 ,  H01L29/739 ,  H01L29/10 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract translation: 功率MOSFET的制造方法在两个连续的抛光步骤之间使用在晶片表面的一部分上的硬掩模膜作为抛光停止器。 在晶片的至少划片区域中存在用于形成沟槽的硬掩模膜的状态下进行嵌入式外延生长之后，通过使用硬掩模膜作为阻挡层进行一次抛光，然后在 去除硬掩模膜。

公开(公告)号：US08921927B2

公开(公告)日：2014-12-30

申请号：US14300327

申请日：2014-06-10

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yuya Abiko ,  Junichi Kogure

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US10204987B2

公开(公告)日：2019-02-12

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Akio Ichimura ,  Natsuo Yamaguchi ,  Tetsuya Iida

IPC: H01L21/31 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US10141397B2

公开(公告)日：2018-11-27

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio Ichimura ,  Satoshi Eguchi ,  Tetsuya Iida ,  Yuya Abiko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US09520318B2

公开(公告)日：2016-12-13

申请号：US14995996

申请日：2016-01-14

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yoshito Nakazawa

IPC: H01L21/761 ,  H01L21/265 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.

Abstract translation: 一种制造半导体器件的方法，该半导体器件包括形成在晶胞区外的单元区域和周边区域，包括以下步骤：（a）提供包括在其主表面上形成的第一导电类型的第一外延层的半导体衬底（ b）掺杂较低带隙杂质，以在掺杂到单元区域内的第一外延层之后使带隙小于第一外延层的带隙，从而形成较低带隙区域，（c）在步骤 （b）中，形成与第一导电类型相反的导电类型的多个第一导电类型的第一列区域，以便在从单元区域扩展到第一导电类型的第一外延层中彼此分离 周边区域，（d）在步骤（c）之后，形成第二外延层。

公开(公告)号：US09269767B2

公开(公告)日：2016-02-23

申请号：US14743897

申请日：2015-06-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

公开(公告)号：US09252262B2

公开(公告)日：2016-02-02

申请号：US14590937

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yoshito Nakazawa

IPC: H01L29/12 ,  H01L29/38 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

Abstract: The reliability of a semiconductor device including a power semiconductor element is improved. The basic idea in embodiments is to make the band gap of a cell region smaller than the band gap of a peripheral region. Specifically, a lower band gap region having a smaller band gap than the band gap of an epitaxial layer is formed in the cell region. In addition, a higher band gap region having a larger band gap than the band gap of the epitaxial layer is formed in the peripheral region.

Abstract translation: 提高了包括功率半导体元件的半导体器件的可靠性。 实施例中的基本思想是使单元区域的带隙小于外围区域的带隙。 具体地，在单元区域中形成具有比外延层的带隙小的带隙的较低带隙区域。 此外，在周边区域中形成具有比外延层的带隙大的带隙的较高带隙区域。

公开(公告)号：US09660070B2

公开(公告)日：2017-05-23

申请号：US14993671

申请日：2016-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

公开(公告)号：US09041070B2

公开(公告)日：2015-05-26

申请号：US14109208

申请日：2013-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi Eguchi ,  Yoshito Nakazawa ,  Tomohiro Tamaki

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

公开(公告)号：US08796094B2

公开(公告)日：2014-08-05

申请号：US14149909

申请日：2014-01-08

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yuya Abiko ,  Junichi Kogure

IPC: H01L21/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.