公开(公告)号：US08921927B2

公开(公告)日：2014-12-30

申请号：US14300327

申请日：2014-06-10

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yuya Abiko ,  Junichi Kogure

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US08796094B2

公开(公告)日：2014-08-05

申请号：US14149909

申请日：2014-01-08

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yuya Abiko ,  Junichi Kogure

IPC: H01L21/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

公开(公告)号：US10204987B2

公开(公告)日：2019-02-12

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Akio Ichimura ,  Natsuo Yamaguchi ,  Tetsuya Iida

IPC: H01L21/31 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US10141397B2

公开(公告)日：2018-11-27

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio Ichimura ,  Satoshi Eguchi ,  Tetsuya Iida ,  Yuya Abiko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US10651277B2

公开(公告)日：2020-05-12

申请号：US16299025

申请日：2019-03-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Natsuo Yamaguchi ,  Satoshi Eguchi

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L21/308 ,  H01L21/265

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

公开(公告)号：US10355122B2

公开(公告)日：2019-07-16

申请号：US15640375

申请日：2017-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Shigeaki Saito ,  Daisuke Taniguchi ,  Natsuo Yamaguchi

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/22 ,  H01L21/225 ,  H01L29/861

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

公开(公告)号：US09997621B2

公开(公告)日：2018-06-12

申请号：US15355469

申请日：2016-11-18

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Hitoshi Matsuura ,  Yuya Abiko

IPC: H01L29/739 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/32 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7396 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/6634

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

公开(公告)号：US09972713B2

公开(公告)日：2018-05-15

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Tetsuya Iida ,  Akio Ichimura ,  Yuya Abiko

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

公开(公告)号：US09905644B2

公开(公告)日：2018-02-27

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya Abiko ,  Satoshi Eguchi ,  Akio Ichimura ,  Natsuo Yamaguchi ,  Tetsuya Iida

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US09786735B2

公开(公告)日：2017-10-10

申请号：US14968004

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Akio Ichimura ,  Satoshi Eguchi ,  Tetsuya Iida ,  Yuya Abiko

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.