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    Power semiconductor device
    3.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US08981469B2

    公开(公告)日：2015-03-17

    申请号：US14037103

    申请日：2013-09-25

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40

    CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

    Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

    Abstract translation: 解决了与各种工艺参数相对较轻的波动引起的n沟道功率MOSFET等相关的问题：源极 - 漏极击穿电压通过靠近p型体区域的端部的击穿而减小 到由该区域的电场浓度引起的活性单元区域与芯片周边部分之间的环状中间区域附近的部分。 为了解决这个问题，在第一导电类型的有源电池区域，芯片外围区域和位于它们之间的中间区域的各个漂移区域中，具有超结构结构的功率半导体器件采取以下措施： 使包括中间区域中的超结构结构的第二导电类型的列区域中的至少一个比其它区域的宽度大。

    Vertical power MOSFET
    7.
    发明授权
    Vertical power MOSFET 有权
    垂直功率MOSFET

    公开(公告)号：US09536943B2

    公开(公告)日：2017-01-03

    申请号：US14027956

    申请日：2013-09-16

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro Tamaki

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16

    CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

    Abstract: Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

    Abstract translation: 具有超级结的垂直功率MOSFET是能够比其他垂直功率MOSFET具有更低导通电阻的器件。 虽然它们具有由于切换操作中的关闭时N型漂移区的快速耗尽而具有高速切换的优点，但是它们可能引起振铃。 本发明提供的具有超结结构的垂直功率MOSFET在栅电极下的第一导电类型漂移区的表面区域具有深度比第二导电类型深的浅底栅重掺杂N型区 并且其浓度高于第一导电类型漂移区域的浓度。

    Vertical power MOSFET
    8.
    发明授权
    Vertical power MOSFET 有权
    垂直功率MOSFET

    公开(公告)号：US09041070B2

    公开(公告)日：2015-05-26

    申请号：US14109208

    申请日：2013-12-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Satoshi Eguchi ,  Yoshito Nakazawa ,  Tomohiro Tamaki

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

    Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

    Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

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