Invention Grant
US09589810B2 Manufacturing method of power MOSFET using a hard mask as a CMP stop layer between sequential CMP steps
有权
在连续CMP步骤之间使用硬掩模作为CMP停止层的功率MOSFET的制造方法
- Patent Title: Manufacturing method of power MOSFET using a hard mask as a CMP stop layer between sequential CMP steps
- Patent Title (中): 在连续CMP步骤之间使用硬掩模作为CMP停止层的功率MOSFET的制造方法
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Application No.: US14950200Application Date: 2015-11-24
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Publication No.: US09589810B2Publication Date: 2017-03-07
- Inventor: Satoshi Eguchi , Daisuki Taniguchi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Womble Carlyle
- Priority: JP2013-008213 20130121
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L21/308 ; H01L23/544 ; H01L21/02 ; H01L29/861 ; H01L29/739 ; H01L29/10 ; H01L21/78 ; H01L23/00
Abstract:
A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.
Public/Granted literature
- US20160079079A1 Manufacturing Method of Power MOSFET Using a Hard Mask as a CMP Stop Layer Between Sequential CMP Steps Public/Granted day:2016-03-17
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