公开(公告)号：US09589810B2

公开(公告)日：2017-03-07

申请号：US14950200

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Daisuki Taniguchi

IPC: H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L23/544 ,  H01L21/02 ,  H01L29/861 ,  H01L29/739 ,  H01L29/10 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract translation: 功率MOSFET的制造方法在两个连续的抛光步骤之间使用在晶片表面的一部分上的硬掩模膜作为抛光停止器。 在晶片的至少划片区域中存在用于形成沟槽的硬掩模膜的状态下进行嵌入式外延生长之后，通过使用硬掩模膜作为阻挡层进行一次抛光，然后在 去除硬掩模膜。