公开(公告)号：US20160343646A1

公开(公告)日：2016-11-24

申请号：US14836501

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Tong Cui

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13563 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/381 ,  H05K3/3426 ,  H05K2201/10704 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/067

Abstract: A package (e.g., wafer level package) that includes a die, a redistribution portion coupled to the die, a first high aspect ratio (HAR) interconnect coupled to the redistribution portion of the package, where the first high aspect ratio (HAR) interconnect comprises a width to height ratio of about at least 1:2, and a first solder interconnect coupled to the first high aspect ratio (HAR) interconnect and the redistribution portion. In some implementations, the first high aspect ratio (HAR) interconnect is a composite interconnect that includes a first conductive core and a first conductive layer that at least partially encapsulates the first conductive core. In some implementations, the first conductive layer is a diffusion barrier.

Abstract translation: 包括管芯，耦合到管芯的再分配部分的封装（例如，晶片级封装），耦合到封装的再分配部分的第一高纵横比（HAR）互连，其中第一高纵横比（HAR）互连 包括大约至少1:2的宽高比，以及耦合到第一高纵横比（HAR）互连和再分配部分的第一焊料互连。 在一些实现中，第一高宽比（HAR）互连是复合互连，其包括第一导电芯和至少部分地封装第一导电芯的第一导电层。 在一些实施方案中，第一导电层是扩散阻挡层。

公开(公告)号：US20140339712A1

公开(公告)日：2014-11-20

申请号：US13898427

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Jianwen Xu

IPC: H01L23/00

CPC classification number: H01L21/561 ,  B23K26/364 ,  B23K26/389 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/31127 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括衬底，耦合到衬底的几个金属和电介质层，以及耦合到几个金属层之一的焊盘。 半导体器件还包括耦合到焊盘的第一金属层和耦合到第一金属再分配层的凸块下金属化层。 半导体器件还包括覆盖半导体器件的第一表面和至少半导体器件的侧部的模层。 在一些实施方案中，模制层是环氧树脂层。 在一些实施方案中，半导体器件的第一表面是半导体器件的顶侧。 在一些实施方案中，模具层覆盖半导体器件的至少侧面部分，使得多个金属层和电介质层中的至少一个的侧部被模具层覆盖。

公开(公告)号：US10141202B2

公开(公告)日：2018-11-27

申请号：US13898427

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Jianwen Xu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L21/311 ,  B23K26/40 ,  B23K26/364 ,  B23K103/16 ,  B23K26/382

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

公开(公告)号：US09806052B2

公开(公告)日：2017-10-31

申请号：US14854039

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  Reynante Tamunan Alvarado

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L24/45 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13012 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder. A method for manufacturing a semiconductor package with such a conductive pillar may include placing a plurality of conductive pillars on a substrate using a stencil process.

公开(公告)号：US09209110B2

公开(公告)日：2015-12-08

申请号：US14272494

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Steve Joseph Bezuk

IPC: H01L23/04 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/4896 ,  H01L21/56 ,  H01L21/76897 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/00012

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，耦合到衬底的第一管芯，耦合到衬底和第一管芯的第一封装层，以及第一封装层中的第二封装层。 第二封装层包括一组配置为作为过孔工作的导线。 在一些实现中，集成器件包括第一封装层中的一组通孔。 在一些实施方案中，集成器件还包括耦合到衬底的第二管芯。 在一些实施方案中，第二封装层位于第一管芯和第二管芯之间。 在一些实施方案中，集成器件还包括第一封装层中的空腔，其中第二封装层位于空腔中。 在一些实施方案中，空腔具有非垂直的壁。 在一些实施方案中，至少一条导线是非垂直的。

公开(公告)号：US09171782B2

公开(公告)日：2015-10-27

申请号：US13960110

申请日：2013-08-06

Applicant: QUALCOMM Incorporated

Inventor： Christine Sung-An Hau-Riege ,  You-Wen Yau ,  Kevin Patrick Caffey ,  Lizabeth Ann Keser ,  Gene Hyde McAllister ,  Reynante Tamunan Alvarado ,  Steve Joseph Bezuk ,  Damion Bryan Gastelum

IPC: H01L27/118 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L23/485 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.

Abstract translation: 一些实施方案提供了一种半导体器件（例如，管芯），其包括衬底，耦合到衬底的几个金属层和电介质层，耦合到多个金属层中的一个的焊盘，耦合到衬垫的第一金属再分布层，以及 耦合到第一金属再分配层的第二金属再分配层。 第二金属再分布层包括钴钨磷材料。 在一些实施方案中，第一金属再分配层是铜层。 在一些实施方案中，半导体器件还包括第一底部浸渍金属化（UBM）层和第二底部金属化（UBM）层。

公开(公告)号：US11545411B2

公开(公告)日：2023-01-03

申请号：US16941487

申请日：2020-07-28

Applicant: QUALCOMM Incorporated

Inventor： Wen Yin ,  Yonghao An ,  Reynante Tamunan Alvarado

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00

Abstract: A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

公开(公告)号：US09806048B2

公开(公告)日：2017-10-31

申请号：US15072315

申请日：2016-03-16

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann Keser ,  David Fraser Rae ,  Reynante Tamunan Alvarado

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01047 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.

公开(公告)号：US20150325496A1

公开(公告)日：2015-11-12

申请号：US14272494

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Steve Joseph Bezuk

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/4896 ,  H01L21/56 ,  H01L21/76897 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/00012

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，耦合到衬底的第一管芯，耦合到衬底和第一管芯的第一封装层，以及第一封装层中的第二封装层。 第二封装层包括一组配置为作为过孔工作的导线。 在一些实现中，集成器件包括第一封装层中的一组通孔。 在一些实施方案中，集成器件还包括耦合到衬底的第二管芯。 在一些实施方案中，第二封装层位于第一管芯和第二管芯之间。 在一些实施方案中，集成器件还包括第一封装层中的空腔，其中第二封装层位于空腔中。 在一些实施方案中，空腔具有非垂直的壁。 在一些实施方案中，至少一条导线是非垂直的。

公开(公告)号：US20150041982A1

公开(公告)日：2015-02-12

申请号：US13960110

申请日：2013-08-06

Applicant: QUALCOMM Incorporated

Inventor： Christine Sung-An Hau-Riege ,  You-Wen Yau ,  Kevin Patrick Caffey ,  Lizabeth Ann Keser ,  Gene H. McAllister ,  Reynante Tamunan Alvarado ,  Steve J. Bezuk ,  Damion Bryan Gastelum

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76841 ,  H01L21/76895 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.

Abstract translation: 一些实施方案提供了一种半导体器件（例如，管芯），其包括衬底，耦合到衬底的几个金属层和电介质层，耦合到多个金属层中的一个的焊盘，耦合到衬垫的第一金属再分布层，以及 耦合到第一金属再分配层的第二金属再分配层。 第二金属再分布层包括钴钨磷材料。 在一些实施方案中，第一金属再分配层是铜层。 在一些实施方案中，半导体器件还包括第一底部浸渍金属化（UBM）层和第二底部金属化（UBM）层。