公开(公告)号：US5453388A

公开(公告)日：1995-09-26

申请号：US132941

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

公开(公告)号：US5373465A

公开(公告)日：1994-12-13

申请号：US132942

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  G11C7/00

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

公开(公告)号：US5317179A

公开(公告)日：1994-05-31

申请号：US764019

申请日：1991-09-23

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

公开(公告)号：US09070679B2

公开(公告)日：2015-06-30

申请号：US12942918

申请日：2010-11-09

申请人： Albert Wu ,  Shiann-Ming Liou ,  Scott Wu

发明人： Albert Wu ,  Shiann-Ming Liou ,  Scott Wu

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/49833 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/00

摘要： Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了半导体封装的配置以及制造半导体封装的相关方法。 制造半导体封装的方法包括将半导体管芯附接到第一衬底，将第二衬底附接到第一衬底，其中半导体管芯被嵌入在第一衬底和第二衬底之间，并且形成电绝缘结构，以基本上 封装半导体管芯，其中在第二衬底附接到第一衬底之后执行形成电绝缘结构。 可以描述和/或要求保护附加实施例。

公开(公告)号：US08796839B1

公开(公告)日：2014-08-05

申请号：US13345449

申请日：2012-01-06

申请人： Sehat Sutardja ,  Albert Wu

发明人： Sehat Sutardja ,  Albert Wu

IPC分类号： H01L23/04

CPC分类号： H01L23/5286 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

摘要翻译： 一种包括电源接地/布置的装置，包括被配置为中央处理单元（CPU）的第一半导体管芯。 电源/接地装置还包括仅提供（i）功率信号和（ii）接地信号中的一个的第一金属层和提供（i）功率信号和（ii）的另一个的第二金属层 ）地面信号。 该装置还包括被配置为耦合到电源/接地装置的存储器的第二半导体管芯。 第二半导体管芯被配置为从电源/接地装置接收功率信号和接地信号。 第二半导体裸片还被配置为经由电源/接地装置向CPU提供信号，并且经由电源/接地布置从CPU接收信号。 第二半导体管芯仅沿着第二半导体管芯的单侧连接到电源/接地装置。

公开(公告)号：US08372692B2

公开(公告)日：2013-02-12

申请号：US13004397

申请日：2011-01-11

申请人： Shiann-Ming Liou ,  Albert Wu

发明人： Shiann-Ming Liou ,  Albert Wu

IPC分类号： H01L21/00 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/82 ,  H01L23/495 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed.

摘要翻译： 本公开的一些实施例提供用于堆叠芯片的设备，系统和方法。 第一芯片可以安装在基板上，其中第一芯片的有源表面背离基板，并且其中第一芯片包括位于第一芯片的有效表面上的多个凸点焊盘，并且导线可以键合 所述多个凸块焊盘的第一凸块焊盘到所述基板。 中间层可以设置在第一芯片的有效表面的至少一部分上，并且中间层内的通孔可以延伸到多个凸块焊盘的第二凸点焊盘。 第二芯片可以设置在中间层上，其中第二芯片的有源表面朝向衬底，并且其中第二芯片包括位于第二芯片的有效表面上的第三凸块焊盘（i），以及（ii） 与中间层中形成的通孔对准。 相应的凸块可以设置在位于第一芯片的有效表面上的（i）第二凸块焊盘中的一个或多个上，以及（ii）位于第二芯片的有效表面上的第三凸块焊盘，并且在通孔内， 其中所述相应的凸块电连接所述第二凸块焊盘与所述第三凸块焊盘。 还描述和要求保护其他实施例。

公开(公告)号：US08330477B1

公开(公告)日：2012-12-11

申请号：US12352439

申请日：2009-01-12

申请人： Albert Wu ,  Chiping Ai ,  Hungchi Chen ,  Bruce Wang ,  Abdul Elaydi

发明人： Albert Wu ,  Chiping Ai ,  Hungchi Chen ,  Bruce Wang ,  Abdul Elaydi

IPC分类号： G01R31/00 ,  G01R31/20

CPC分类号： G01R31/2601 ,  G01R31/318371 ,  G01R31/31919 ,  G06F15/00 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some of the embodiments of the present disclosure provide an integrated circuit (IC) chip comprising a die, a system on chip (SOC) coupled to the die, and an internal test engine included in the SOC and configured to test the die, wherein one or more components within the IC chip may be configured to be tested by an external test engine coupled to the IC chip. Other embodiments are also described and claimed.

摘要翻译： 本公开的一些实施例提供了一种集成电路（IC）芯片，其包括芯片，耦合到管芯的芯片上系统（SOC）和包括在SOC中并被配置为测试裸片的内部测试引擎，其中一个 IC芯片内的多个组件可以被配置为通过耦合到IC芯片的外部测试引擎进行测试。 还描述和要求保护其他实施例。

公开(公告)号：US20120098127A1

公开(公告)日：2012-04-26

申请号：US13277140

申请日：2011-10-19

申请人： Sehat Sutardja ,  Chung Chyung Han ,  Weidan Li ,  Shuhua Yu ,  Chuan-Cheng Cheng ,  Albert Wu

发明人： Sehat Sutardja ,  Chung Chyung Han ,  Weidan Li ,  Shuhua Yu ,  Chuan-Cheng Cheng ,  Albert Wu

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L21/76885 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/45111 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/731 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

摘要翻译： 本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。 第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。 芯片还包括形成在第一金属层上的第二金属层。 第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

公开(公告)号：US20110169163A1

公开(公告)日：2011-07-14

申请号：US12943673

申请日：2010-11-10

申请人： Shiann-Ming Liou ,  Albert Wu

发明人： Shiann-Ming Liou ,  Albert Wu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/11 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/16 ,  H01L2224/11334 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16268 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19104 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种方法，包括在半导体管芯的表面上形成导电结构，将半导体管芯附接到基板，形成模制化合物以封装半导体管芯，在模制化合物中形成开口， 至少部分地暴露导电结构，并且通过模制化合物中的开口将无源部件电耦合到导电结构。 可以描述和/或要求保护其他实施例。

公开(公告)号：US07948818B1

公开(公告)日：2011-05-24

申请号：US12827446

申请日：2010-06-30

申请人： Albert Wu ,  Sehat Sutardja

发明人： Albert Wu ,  Sehat Sutardja

IPC分类号： G11C7/00

CPC分类号： G06F11/0793 ,  G06F11/073 ,  G11C29/789

摘要： An integrated circuit (IC) comprises a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module detects defective memory locations in the memory module, locates redundant memory elements in the memory module, and stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database. Storing said information includes electrically altering at least one of a plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.

摘要翻译： 集成电路（IC）包括存储数据和代码中的至少一个的存储器模块。 存储器修复数据库存储与缺陷存储器地址有关的数据。 存储器控制模块检测存储器模块中的缺陷存储器位置，将冗余存储器元件定位在存储器模块中，并且存储将缺陷存储器位置的存储器地址与冗余存储器元件关联在存储器修复数据库中的信息。 存储所述信息包括电改变多个电保险丝中的至少一个。 冗余存储器解码器模块接收信息并将存储器地址物理地映射到冗余存储器位置。