公开(公告)号：US5959467A

公开(公告)日：1999-09-28

申请号：US938250

申请日：1997-09-26

Applicant: Joseph G. Nolan, III ,  John C. Holst ,  Donald A. Draper

Inventor： Joseph G. Nolan, III ,  John C. Holst ,  Donald A. Draper

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/14 ,  G11C11/418 ,  G11C29/02 ,  G11C29/32 ,  G11C29/50 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099 ,  H03K19/177

CPC classification number: G11C29/026 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/14 ,  H03K5/13 ,  H03L7/08 ,  G11C11/401 ,  G11C11/41 ,  G11C16/04 ,  G11C17/14 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/0995

Abstract: The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.

Abstract translation: 本发明公开了一种差分逻辑电路和感测方法，其提供比现有技术更高的速度和更高密度的差分感测。 将一个或多个输入信号提供给逻辑阵列，并且从逻辑阵列产生两个输出信号，其中逻辑阵列的一个输出信号是位线，逻辑阵列的一个输出信号是位线，如 参考信号，其中两个信号作为输入信号提供给具有二进制输出信号的差分读出放大器。 位线和位线线被预充电到相同的电压电平，并且具有小于填充驱动强度的受控输入源极接地晶体管耦合到位线。 源极接地晶体管耦合到逻辑阵列的每个输入信号，并且通过将源极接地晶体管的漏极耦合到位线而可编程到位线。 具有栅极和漏极但没有源极的相应的无源晶体管被耦合到逻辑阵列的每个输入信号，并且可通过将无源晶体管的漏极耦合到位 - 线。 源极接地晶体管和相应的无源晶体管被编程相同地在位线和位线上提供基本相同的电容负载。

公开(公告)号：US5790461A

公开(公告)日：1998-08-04

申请号：US905034

申请日：1997-08-01

Applicant: John C. Holst

Inventor： John C. Holst

IPC: G11C7/00 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C7/00

Abstract: Control circuitry for a register file is provided which allows immediate or rapid output of input write data by bypassing the need to store the data and then read it out of the register file. In each pairing of memory cells, the read line is coupled to both the storage cell and to the write line. The connection to the write line is configured so that, when the connection is activated, such as by turning on a transistor, the magnitude of the data signal provided from the write line to the read line is large enough to overpower whatever signal is being output to the read line from the memory cell. In this way, when the connection from the write line to the read line is activated, the write line will output the information on the read line, rather than the information in the storage cell. The information on the read line can then be output onto the write line without the information first being stored in the memory cell. This is advantageous when the write data is available at a time when its validity is unknown. Preferably, the device is further configured to permit writing of the data from the write line into the memory cell once the validity of the data is ascertained, e.g., under control of a word line.

Abstract translation: 提供了用于寄存器文件的控制电路，其允许通过绕过存储数据的需要，然后将其从寄存器文件中读出来，立即或快速输出输入写入数据。 在存储器单元的每个配对中，读取线耦合到存储单元和写入线两者。 与写入线的连接被配置为使得当连接被激活时，例如通过接通晶体管，从写入线到读取线提供的数据信号的大小足够大以使所有信号被输出 到存储单元的读取行。 以这种方式，当从写入线到读取线的连接被激活时，写入线将输出读取线上的信息，而不是存储单元中的信息。 然后可以将读取线上的信息输出到写入线上，而不会先将信息存储在存储器单元中。 当写入数据在其有效性未知的时间可用时，这是有利的。 优选地，所述设备还被配置为一旦确定数据的有效性，例如在字线的控制下，则允许将数据从写入线写入存储单元。

公开(公告)号：US06191034B1

公开(公告)日：2001-02-20

申请号：US09286401

申请日：1999-04-05

Applicant: Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

Inventor： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC: H01L2144

CPC classification number: H01L21/76892 ,  H01L21/32139

Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Abstract translation: 在导电线图案中形成最小间隙或空间的方法，用于通过首先在通过常规光学平版印刷在导电线上的绝缘层中形成开口，随后在开口中形成减小开口的侧壁，从而增加集成电路的密度， 并且使用所述侧壁作为掩模，优选地通过蚀刻除去所述导电线图案的大小与所述减小的开口大致相等的部分。

公开(公告)号：US5844836A

公开(公告)日：1998-12-01

申请号：US822518

申请日：1997-03-24

Applicant: Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

Inventor： Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104

Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Abstract translation: 在存储节点处具有增加的单元电容的静态随机存取存储器（SRAM）单元利用电容结构。 电容结构包括多晶硅导电线与钨局部互连之间的电介质材料。 多晶硅板各自连接到与SRAM单元相关联的横向晶体管的漏极。 可以在局部互连和多晶硅导电线之间沉积诸如二氧化硅的电介质材料。 电容器结构设置在与SRAM单元相关联的第一和第二N沟道下拉晶体管之间。

公开(公告)号：US5796651A

公开(公告)日：1998-08-18

申请号：US858589

申请日：1997-05-19

Applicant: Stephen C. Horne ,  Richard K. Klein ,  Asim A. Selcuk ,  Nicholas John Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst

Inventor： Stephen C. Horne ,  Richard K. Klein ,  Asim A. Selcuk ,  Nicholas John Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst

IPC: G11C8/08 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.

Abstract translation: 存储器件在读取操作期间使用减少的字线电压。 存储器件包括存储单元和用于访问单元的通过晶体管。 该单元包括耦合到具有与传输晶体管基本相同的导电性的下拉晶体管的存储节点。 驱动电路在读取操作期间产生降低的字线电压以激活传输晶体管。 减小的字线电压具有小于用于激活下拉晶体管的偏置电压的幅度的幅度。

公开(公告)号：US07026691B1

公开(公告)日：2006-04-11

申请号：US10042732

申请日：2001-04-25

Applicant: Craig S. Sander ,  Rich K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christoper A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

Inventor： Craig S. Sander ,  Rich K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christoper A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC: H01L31/113 ,  H01L31/119 ,  H01L23/48

CPC classification number: H01L29/78 ,  H01L21/2257 ,  H01L21/28123 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Abstract translation: 一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

公开(公告)号：US06420767B1

公开(公告)日：2002-07-16

申请号：US09605920

申请日：2000-06-28

Applicant: Srinath Krishnan ,  John C. Holst ,  Bin Yu

Inventor： Srinath Krishnan ,  John C. Holst ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/78621 ,  H01L29/7841 ,  H01L29/78612

Abstract: A transistor structure is provided comprising a source region having a N+ source region and a N− lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N− lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N− lightly doped source region and N− lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.

Abstract translation: 提供一种晶体管结构，其包括具有N +源极区域和N-轻掺杂源极区域的源极区域。 该结构还包括具有N +漏极区域和N-轻掺杂漏极区域的漏极区域。 提供了P ++重掺杂区域。 P ++区域与N-轻掺杂源区域和N-轻掺杂漏极区域中的至少一个的至少一部分一起存在。 P +体区域位于器件的栅极之下以及源极和漏极区域之间。 P +⇄重掺杂区域在器件区域和器件的栅极之间提供电容耦合，并与器件的结电容形成电容分压器。

公开(公告)号：US06213869B1

公开(公告)日：2001-04-10

申请号：US09309105

申请日：1999-05-10

Applicant: Bin Yu ,  John C. Holst

Inventor： Bin Yu ,  John C. Holst

IPC: H01L218249

CPC classification number: H01L29/78615 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/78 ,  H01L29/7841

Abstract: A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling capacitor is designed such that a BJT (Bipolar Junction Transistor) connected in parallel with the MOSFET turns on when the MOSFET turns on. In addition such a design of the coupling capacitor lowers the magnitude of the threshold voltage of the MOSFET when the MOSFET is turned on. Furthermore, the capacitance of the coupling capacitor is designed such that the magnitude of the threshold voltage of the MOSFET is raised when the MOSFET is turned off. Thus, the MOSFET type device of the present invention has both higher drive current when the MOSFET is turned on and lower steady state power dissipation when the MOSFET is turned off with a variable threshold voltage.

Abstract translation: 耦合电容器耦合在MOSFET（金属氧化物半导体场效应晶体管）的栅极和体区之间。 MOSFET的体区电气隔离以形成浮体区域。 耦合电容器的电容设计成使得当MOSFET导通时，与MOSFET并联连接的BJT（双极结晶体管）导通。 此外，当MOSFET导通时，耦合电容的这种设计降低了MOSFET的阈值电压的幅度。 此外，耦合电容器的电容被设计成使得当MOSFET被断开时MOSFET的阈值电压的幅度上升。 因此，本发明的MOSFET型器件在MOSFET导通时具有较高的驱动电流，并且当MOSFET以可变阈值电压关断时具有较低的稳态功耗。

公开(公告)号：US6046088A

公开(公告)日：2000-04-04

申请号：US985400

申请日：1997-12-05

Applicant: Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

Inventor： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

Abstract: A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

Abstract translation: 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

公开(公告)号：US08270399B2

公开(公告)日：2012-09-18

申请号：US12260841

申请日：2008-10-29

Applicant: John C. Holst ,  William L. Lynch

Inventor： John C. Holst ,  William L. Lynch

IPC: H04L12/50

CPC classification number: H04L12/66 ,  H04L45/00 ,  H04L45/54 ,  H04L45/60

Abstract: A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Abstract translation: 包括包括多个级的查找执行单元的路由器，分层布置的转发表存储器，包括可寻址扇区，块和条目，以及具有地址横栏的交叉开关，用于选择性地将多个级中的一个级联到 存储器，使得可以读取来自扇区的数据。 在一个示例中，多个级中的任何一级可以选择性地和动态地耦合到转发表存储器的任何一个扇区，以便向存储器的特定扇区提供地址以从其读取数据。