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    Soft error robust low power latch device layout techniques
    1.
    发明授权
    Soft error robust low power latch device layout techniques 有权
    软错误鲁棒的低功率锁存器件布局技术

    公开(公告)号：US08547155B2

    公开(公告)日：2013-10-01

    申请号：US13214681

    申请日：2011-08-22

    Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

    Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

    IPC: H03K3/02

    CPC classification number: H03K3/0375

    Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

    Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。

    Soft Error Robust Low Power Latch Device Layout Techniques
    2.
    发明申请
    Soft Error Robust Low Power Latch Device Layout Techniques 有权
    软错误鲁棒低功率锁存器布局技术

    公开(公告)号：US20130049835A1

    公开(公告)日：2013-02-28

    申请号：US13214681

    申请日：2011-08-22

    Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

    Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

    IPC: H03K3/289

    CPC classification number: H03K3/0375

    Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

    Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。

    High-speed lateral bipolar device in SOI process
    3.
    发明授权
    High-speed lateral bipolar device in SOI process 有权
    SOI工艺中的高速横向双极器件

    公开(公告)号：US06376880B1

    公开(公告)日：2002-04-23

    申请号：US09406451

    申请日：1999-09-27

    Applicant: John C. Holst

    Inventor： John C. Holst

    IPC: H01L2781

    CPC classification number: H01L29/66265 ,  H01L29/7317

    Abstract: A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive material overlies the insulating layer and makes electrical contact with the semiconductor layer through the contact hole, thereby forming a base contact. The semiconductor layer has a first conductivity type in a central region which substantially underlies the conductive material, and has a second conductivity type in regions adjacent the central region. The first region forms a base region and the adjacent regions form a collector region and an emitter region, respectively. A method of forming a lateral bipolar transistor device is also disclosed. The method includes forming a semiconductor layer over an insulating material and forming an insulating layer over the semiconductor material. A base contact hole is then formed in the insulating layer and a conductive base contact region is formed over a portion of the insulating layer. The base contact region overlies the base contact hole and makes an electrical connection to a middle portion of the semiconductor layer, which corresponds to a base region. Lastly, a collector region and an emitter region are formed on opposite sides of the base region such that the collector region and the emitter region are adjacent the base region, respectively.

    Abstract translation: 横向双极晶体管包括覆盖电绝缘材料的半导体层和覆盖半导体层中心部分的绝缘层。 接触孔位于绝缘层中，导电材料覆盖绝缘层，并通过接触孔与半导体层电接触，从而形成基极接触。 半导体层在中心区域具有基本上位于导电材料下面的第一导电类型，并且在邻近中心区域的区域中具有第二导电类型。 第一区域形成基极区域，相邻区域分别形成集电极区域和发射极区域。 还公开了一种形成横向双极晶体管器件的方法。 该方法包括在绝缘材料上形成半导体层并在半导体材料上形成绝缘层。 然后在绝缘层中形成基部接触孔，并且在绝缘层的一部分上形成导电性基极接触区域。 基部接触区域覆盖在基部接触孔上，并且与半导体层的与基部区域对应的中间部分形成电连接。 最后，在基极区域的相对侧上形成集电极区域和发射极区域，使得集电极区域和发射极区域分别与基极区域相邻。

    SOI with conductive metal substrate used as VSS connection
    4.
    发明授权
    SOI with conductive metal substrate used as VSS connection 有权
    SOI与导电金属基板作为VSS连接

    公开(公告)号：US6153912A

    公开(公告)日：2000-11-28

    申请号：US427139

    申请日：1999-10-25

    Applicant: John C. Holst

    Inventor： John C. Holst

    IPC: H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78639

    Abstract: An SOI transistor structure and SOI circuit is disclosed. The SOI transistor structure includes a conductive base layer and an insulating layer overlying the conductive base layer. A semiconductor layer overlies the insulating layer and includes a source region and a drain region therein with a channel region disposed therebetween. A conductive gate region overlies generally the channel region of the semiconductor layer. The SOI circuit includes a conductive base layer and an insulating layer overlying the conductive base layer. A semiconductor layer overlies the insulating layer. A first circuit structure and a second circuit structure are formed in a first region and second region of the semiconductor layer, respectively. A conductive contact region extends through the insulating layer and electrically connects at least one of the first circuit structure and the second circuit structure to the conductive base layer.

    Abstract translation: 公开了SOI晶体管结构和SOI电路。 SOI晶体管结构包括导电基底层和覆盖导电基底层的绝缘层。 半导体层覆盖在绝缘层上，并且包括其中设置有沟道区的源区和漏区。 导电栅极区域大致覆盖半导体层的沟道区域。 SOI电路包括导电基底层和覆盖导电基底层的绝缘层。 半导体层覆盖绝缘层。 第一电路结构和第二电路结构分别形成在半导体层的第一区域和第二区域中。 导电接触区延伸穿过绝缘层，并将第一电路结构和第二电路结构中的至少一个电连接到导电基层。

    Start-up circuit for write selects and equilibrates
    6.
    发明授权
    Start-up circuit for write selects and equilibrates 有权
    启动电路用于写入选择和平衡

    公开(公告)号：US06084454A

    公开(公告)日：2000-07-04

    申请号：US140602

    申请日：1998-08-26

    Applicant: John C. Holst

    Inventor： John C. Holst

    IPC: H03K17/22

    CPC classification number: H03K17/223

    Abstract: Some logic circuits preferentially reside in a particular state. Advantages are gained by a circuit that forces the circuit to the preferential state but allows the preferred state to be overridden. A node in the logic circuit is driven to a particular state, in one embodiment, by a pull-up transistor connected to a pull-down transistor that respectively drive the node to a high state and a low state. A keeper circuit is connected to the node and drives the node to the preferred state unless overpowered by the pull-up transistor and the pull-down transistor. The keeper circuit drives the node using a transistor that is weaker than the pull-up transistor and weaker than the pull-down transistor. A startup-circuit is connected to the node and drives the node to the preferred state when the node powers-up in the nonpreferred state. The start-up circuit drives the node using a transistor that is weaker than the keeper circuit transistor.

    Abstract translation: 一些逻辑电路优先驻留在特定状态。 通过电路获得优点，该电路迫使电路处于优先状态，但允许优先状态被覆盖。 在一个实施例中，逻辑电路中的节点被驱动到特定状态，该上拉晶体管连接到分别将节点驱动到高状态和低状态的下拉晶体管。 保持器电路连接到节点，并且将节点驱动到优选状态，除非被上拉晶体管和下拉晶体管过大。 保持器电路使用比上拉晶体管更弱的晶体管驱动节点，并且比下拉晶体管更弱。 当节点在非优先状态下加电时，启动电路连接到节点并将节点驱动到优选状态。 启动电路使用比保持器电路晶体管更弱的晶体管来驱动节点。

    Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
    8.
    发明授权
    Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device 失效
    基于寄存器的冗余电路和在半导体存储器件中内置自修复的方法

    公开(公告)号：US5920515A

    公开(公告)日：1999-07-06

    申请号：US938062

    申请日：1997-09-26

    Applicant: Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

    Inventor： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/84 ,  G11C29/844

    Abstract: A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.

    Abstract translation: 具有内置自修复（BISR）的半导体存储器阵列包括与故障行地址存储相关联的冗余电路以驱动冗余行字线，从而避免替代地址的供应和正常解码。 NOT比较器逻辑将由BISR电路生成和存储的故障行地址与提供给存储器阵列的行地址进行比较。 与NOT比较并行配置的TRUE比较器同时将缺陷行地址信号与提供的行地址进行比较。 由于在没有设置和保持时间约束的情况下，在动态逻辑中不快速执行比较，所以对正常（非冗余）行解码路径的定时影响是可以忽略的，并且由于真正的比较虽然潜在地比NOT比较慢，但是它自身识别冗余行地址 因此不需要对所选字线解码采用N位地址，冗余行寻址是快速的并且不会不利地降低自修复的半导体存储器阵列的性能。 通过在预解码电路级提供冗余处理，而不是在初始地址替换阶段，改进了根据本发明的BISR存储器阵列的访问时间。

    Comparator cell for use in a content addressable memory
    9.
    发明授权
    Comparator cell for use in a content addressable memory 失效
    用于内容可寻址存储器的比较器单元

    公开(公告)号：US5598115A

    公开(公告)日：1997-01-28

    申请号：US385496

    申请日：1995-02-08

    Applicant: John C. Holst

    Inventor： John C. Holst

    IPC: G06F12/10 ,  G11C15/04 ,  H03K19/094

    CPC classification number: G06F12/1027 ,  G11C15/04

    Abstract: A content-addressable memory wherein match transistors are prevented from discharging a match line by either placing transistors in series with the match transistors and only turning them on during a match sensing period, or a match sense line which is driven near the precharge voltage of the match line until the match sensing period. The match sensing line also provides charging current to recharge the match line. For some applications, a differential match line amplifier is used to detect matches and mismatches. The match sense line can be used with a CAM having a four-transistor comparator. The invention is also applicable to match lines in programmable-array logic (PAL) cells, and for either NMOS or PMOS circuits.

    Abstract translation: 一种可内容寻址的存储器，其中通过将晶体管与匹配晶体管串联放置而防止匹配晶体管放电，并且仅在匹配感测周期期间将其导通，或者在匹配感测周期内驱动接近预充电电压的匹配感测线 匹配线直到匹配感测周期。 匹配感测线还提供充电电流来对匹配线进行充电。 对于某些应用，使用差分匹配线放大器来检测匹配和不匹配。 匹配检测线可以与具有四晶体管比较器的CAM一起使用。 本发明也适用于在可编程阵列逻辑（PAL）单元以及NMOS或PMOS电路中匹配线路。

    Decoder scheme for fully associative translation-lookaside buffer
    10.
    发明授权
    Decoder scheme for fully associative translation-lookaside buffer 失效
    完全关联翻译后备缓冲区的解码器方案

    公开(公告)号：US5299147A

    公开(公告)日：1994-03-29

    申请号：US23783

    申请日：1993-02-22

    Applicant: John C. Holst

    Inventor： John C. Holst

    IPC: G06F12/10 ,  G11C11/413 ,  G11C15/00 ,  G11C13/00

    CPC classification number: G11C11/413 ,  G06F12/1027

    Abstract: A fully associative translation lookaside buffer (TLB) using a content addressable memory (CAM) array to store virtual addresses and a static random access memory (SRAM) array to store corresponding physical addresses. The TLB incorporates a logic circuit that allows the SRAM to be accessed during both associative and non-associative modes by word lines that are strictly a function of corresponding match lines. Additionally, the logic circuit incorporated in the TLB does not introduce any additional delay in outputting the physical address from the SRAM during the associative mode.

    Abstract translation: 使用内容可寻址存储器（CAM）阵列存储虚拟地址的完全关联翻译后备缓冲器（TLB）和用于存储相应物理地址的静态随机存取存储器（SRAM）阵列。 TLB包含一个逻辑电路，允许在关联和非关联模式期间通过绝对是对应匹配线的函数的字线来访问SRAM。 此外，并入TLB中的逻辑电路在关联模式期间不会从SRAM输出物理地址引入任何额外的延迟。

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