公开(公告)号：US08689081B2

公开(公告)日：2014-04-01

申请号：US13304838

申请日：2011-11-28

Applicant: Andy Yu ,  Pierre Chor-Fung Chia ,  ShiJie Wen ,  Jie Xue

Inventor： Andy Yu ,  Pierre Chor-Fung Chia ,  ShiJie Wen ,  Jie Xue

IPC: G11C29/00

CPC classification number: G06F11/1048

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract translation: 提供技术用于对位序列中的错误进行分类和纠正。 在存储器控制装置中，请求访问存储在存储器组件的位序列数据库中并与地址相关联的第一位序列。 在第一比特序列中检测到错误，并且将与比特序列相关联的地址与存储在内容可寻址存储器组件的地址数据库中的地址进行比较，以确定是否存在匹配。 当有匹配时，错误被分类为硬比特错误。 当没有匹配时，错误被分类为软比特错误。

公开(公告)号：US20120032693A1

公开(公告)日：2012-02-09

申请号：US12849426

申请日：2010-08-03

Applicant: Jie Xue ,  ShiJie Wen

Inventor： Jie Xue ,  ShiJie Wen

IPC: G01R27/08 ,  H01L23/498

CPC classification number: G01R31/2896 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/00

Abstract: A method is provided in which an impedance is measured between a first of a plurality of seal ring contact pads and a ground contact pad coupled to a semiconductor substrate of a semiconductor device. The first impedance value is obtained from the measured impedance, and the first impedance value is compared with a reference impedance value to determine whether a structural defect is present in the semiconductor device based on whether the first impedance value is greater than the reference impedance value.

Abstract translation: 提供了一种方法，其中在多个密封环接触焊盘中的第一个与耦合到半导体器件的半导体衬底的接地焊盘之间测量阻抗。 从测量的阻抗获得第一阻抗值，并且将第一阻抗值与参考阻抗值进行比较，以基于第一阻抗值是否大于参考阻抗值来确定半导体器件中是否存在结构缺陷。

公开(公告)号：US08547155B2

公开(公告)日：2013-10-01

申请号：US13214681

申请日：2011-08-22

Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

IPC: H03K3/02

CPC classification number: H03K3/0375

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。

公开(公告)号：US20130139033A1

公开(公告)日：2013-05-30

申请号：US13304838

申请日：2011-11-28

Applicant: Andy Yu ,  Pierre Chor-Fung Chia ,  ShiJie Wen ,  Jie Xue

Inventor： Andy Yu ,  Pierre Chor-Fung Chia ,  ShiJie Wen ,  Jie Xue

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract translation: 提供技术用于对位序列中的错误进行分类和纠正。 在存储器控制装置中，请求访问存储在存储器组件的位序列数据库中并与地址相关联的第一位序列。 在第一比特序列中检测到错误，并且将与比特序列相关联的地址与存储在内容可寻址存储器组件的地址数据库中的地址进行比较，以确定是否存在匹配。 当有匹配时，错误被分类为硬比特错误。 当没有匹配时，错误被分类为软比特错误。

公开(公告)号：US20130049835A1

公开(公告)日：2013-02-28

申请号：US13214681

申请日：2011-08-22

Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

IPC: H03K3/289

CPC classification number: H03K3/0375

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。