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    REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
    1.
    发明申请
    REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME 有权
    使用相同的维修电路和半导体装置

    公开(公告)号：US20160099079A1

    公开(公告)日：2016-04-07

    申请号：US14599906

    申请日：2015-01-19

    申请人： SK hynix Inc.

    发明人： Ga Ram PARK

    IPC分类号： G11C29/00 ,  G11C17/18 ,  G11C17/16

    CPC分类号： G11C29/78 ,  G11C17/16 ,  G11C17/18 ,  G11C29/844 ,  G11C2029/4402

    摘要： A repair circuit includes a fuse set latch array including a plurality of fuse set latches, and configured to store fuse informations in target fuse latches selected among the plurality of fuse set latches in response to fuse latch select signals; a fuse information control unit configured to generate the fuse latch select signals by using boot-up source signals generated by differently combining boot-up mode region select informations according to a region determination signal; and a repair processing unit configured to compare an address inputted from an exterior and the fuse informations, and access a normal memory cell corresponding to the external address or a redundant memory cell.

    摘要翻译： 维修电路包括：熔丝组锁存阵列，其包括多个熔丝组锁存器，并且被配置为响应于熔丝锁存选择信号，在多个熔丝组锁存器中选择的目标熔丝锁存器中存储熔丝信息; 熔丝信息控制单元，被配置为通过使用通过根据区域确定信号不同地组合启动模式区域选择信息而生成的引导源信号来生成熔丝锁存选择信号; 以及修复处理单元，被配置为比较从外部输入的地址和熔丝信息，以及访问与外部地址或冗余存储单元对应的正常存储单元。

    System and method for implementing row redundancy with reduced access time and reduced device area
    2.
    发明授权
    System and method for implementing row redundancy with reduced access time and reduced device area 有权
    实现行冗余的系统和方法，减少了访问时间，减少了设备面积

    公开(公告)号：US07609569B2

    公开(公告)日：2009-10-27

    申请号：US11941994

    申请日：2007-11-19

    申请人： Michael T. Fragano ,  Harold Pilo

    发明人： Michael T. Fragano ,  Harold Pilo

    IPC分类号： G11C7/00

    CPC分类号： G11C29/846 ,  G11C29/844

    摘要： A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.

    摘要翻译： 用于在集成电路存储器件中实现行冗余的系统包括具有字线，位线和存储单元器件的一个或多个主子阵列，所述一个或多个主子阵列中的每一个包括与其相关联的一组支持电路。 离散的冗余子阵列与主子阵列相关联，并且还包括与其相关联的一组支持电路。 一个共同的全局位线由主子阵列和冗余子阵列共享，并且冗余转向控制电路与主子阵列和冗余子阵列相关联。 冗余转向控制电路被配置为使得与冗余转向控制电路执行的地址比较操作并行执行主子阵列和冗余子阵列的字线激活。

    Reduced power redundancy address decoder and comparison circuit
    6.
    发明授权
    Reduced power redundancy address decoder and comparison circuit 有权
    减少冗余地址解码器和比较电路

    公开(公告)号：US06868019B2

    公开(公告)日：2005-03-15

    申请号：US10613305

    申请日：2003-07-02

    申请人： Christian N. Mohr ,  Scott E. Smith

    发明人： Christian N. Mohr ,  Scott E. Smith

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/83 ,  G11C29/844

    摘要： A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

    摘要翻译： 一种用于存储器的冗余地址解码器，其具有被分割成多个存储块的至少一组存储器。 冗余地址解码器包括耦合到存储映射到存储器平面的冗余存储器的地址的相应可编程元件块的多个冗余比较电路。 冗余地址解码器还包括耦合到冗余比较电路中的每一个的冗余驱动器选择逻辑，以激活冗余比较电路中的所选择的一个，用于将对应于存储器位置的存储器地址的一部分与相应可编程元件的编程地址进行比较 块，这导致对存储器设备的列访问的功率降低。 冗余驱动器的选择基于存储器位置所在的存储体。

    Configuration for implementing redundancy for a memory chip
    7.
    发明申请
    Configuration for implementing redundancy for a memory chip 有权
    用于实现存储芯片冗余的配置

    公开(公告)号：US20020012281A1

    公开(公告)日：2002-01-31

    申请号：US09907783

    申请日：2001-07-18

    发明人： Helmut Fischer ,  Helmut Kandolf ,  Stefan Lammers

    IPC分类号： G11C029/00

    CPC分类号： G11C29/80 ,  G11C29/812 ,  G11C29/844

    摘要： The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.

    摘要翻译： 本发明涉及一种用于实现存储器芯片的冗余的配置，其中熔丝组经由冗余预解码器连接到比较器，使得预解码的地址可以在比较器中相互比较，而未解码的地址可以存储在保险丝中 银行。 这提供了一个低功耗和节省空间的设计。

    Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency
    9.
    发明授权
    Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency 失效
    具有用于提高操作频率的解码外围电路的半导体存储器件

    公开(公告)号：US5640365A

    公开(公告)日：1997-06-17

    申请号：US524630

    申请日：1995-09-07

    申请人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

    发明人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

    IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/842 ,  G11C29/844 ,  G11C7/22 ,  G11C8/18

    摘要： A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

    摘要翻译： 在存储单元阵列附近提供将存储单元阵列中与所选存储单元对应的数据存储的数据寄存器。 从数据寄存器中选择数据的解码器响应于与确定操作周期的时钟信号同步地访问存储器单元的地址信号开始解码。 在时钟信号的运算周期的前半部分中，解码器响应于与前一操作周期中确定的地址信号对应的信号输出信号。 根据解码器的输出，选择数据寄存器。 在操作期间的后半部分，将与下一个操作期间的新的地址信号对应的信号传送到解码器。 通过这样做，使解码器中的输出控制信号与驱动地址信号的信号同步，使得能够选择合适的地址。

    Semiconductor memory device capable of driving word lines at high speed
    10.
    发明授权
    Semiconductor memory device capable of driving word lines at high speed 失效
    能够高速驱动字线的半导体存储器件

    公开(公告)号：US5579268A

    公开(公告)日：1996-11-26

    申请号：US580885

    申请日：1995-12-29

    申请人： Dong-Il Seo ,  Tae-Seong Jang

    发明人： Dong-Il Seo ,  Tae-Seong Jang

    IPC分类号： G11C8/08 ,  G11C29/00 ,  G11C11/40

    CPC分类号： G11C29/844 ,  G11C8/08 ,  G11C29/781

    摘要： A semiconductor memory device for driving word lines at high speed has a word line signal generating circuit for receiving a predecoded signal of a row address, and power source supply circuit for supplying the output signal of the word line signal generating circuit to a word line as source power. The device includes a normal word line decoder for receiving the predecoded signal and the output signal of the power source supplying circuit, respectively and for selecting a normal word line; a spare word line decoder for receiving the predecoded signal and the output signal of the power source supply circuit, respectively and for selecting a spare word line; and a redundancy enabling circuit connected to the spare word line decoder and the normal word line decoder for determining whether the normal word line is selected.

    摘要翻译： 用于高速驱动字线的半导体存储器件具有用于接收行地址的预解码信号的字线信号发生电路和用于将字线信号发生电路的输出信号提供给字线的电源供应电路， 源功率 该装置包括用于分别接收预解码信号和电源供给电路的输出信号的正常字线解码器，用于选择正常字线; 用于分别接收所述预解码信号和所述电源供给电路的输出信号的备用字线解码器，用于选择备用字线; 以及连接到备用字线解码器和通常字线解码器的冗余使能电路，用于确定是否选择了正常字线。