公开(公告)号：US06911846B1

公开(公告)日：2005-06-28

申请号：US09019278

申请日：1998-02-05

Applicant: James S. Blomgren ,  Terence M. Potter ,  Stephen C. Horne ,  Michael R. Seningen ,  Anthony M. Petro

Inventor： James S. Blomgren ,  Terence M. Potter ,  Stephen C. Horne ,  Michael R. Seningen ,  Anthony M. Petro

IPC: G11C8/10 ,  G11C11/56 ,  H03K19/003 ,  H03K19/096

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C8/10 ,  H03K19/00346 ,  H03K19/0963

Abstract: The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Abstract translation: 本发明包括一种用于集成电路（IC）的方法和装置，其使用N个信号中的1个来减少电路的导线以有效电容。 本发明包括一个逻辑树电路，其耦合到N个输入信号的第一个1，N个输入信号的第二个1和N个输出信号中的1个，其中N个信号的1个将信号的导线降低到有线电容。 本发明的其它实施例包括使用2个信号中的1个，3个信号中的1个，4个信号中的1个，以及信号中的一个和一个有效的8个信号中的1个信号。

公开(公告)号：US6104642A

公开(公告)日：2000-08-15

申请号：US207806

申请日：1998-12-09

Applicant: James S. Blomgren ,  Terence M. Potter ,  Michael R. Seningen ,  Stephen C. Horne

Inventor： James S. Blomgren ,  Terence M. Potter ,  Michael R. Seningen ,  Stephen C. Horne

IPC: G06F1/08 ,  G06F5/01 ,  G06F7/02 ,  G06F7/49 ,  G06F7/50 ,  G06F7/544 ,  G06F17/50 ,  G11C8/00 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/096 ,  H03K19/21 ,  G11C7/00

CPC classification number: G06F7/5443 ,  G06F1/08 ,  G06F17/5045 ,  G06F5/015 ,  G06F7/02 ,  G06F7/026 ,  G06F7/49 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  G11C8/00 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  H03K19/0002 ,  H03K19/00346 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/0813 ,  H03K19/0963 ,  H03K19/215 ,  G06F2207/3824 ,  G06F7/483 ,  G06F7/508 ,  G11C7/1006

Abstract: The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.

Abstract translation: 本发明是一种用于存储信息的寄存器单元的方法和装置。 该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。 多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。 复用器还被配置为提供存储数据，第一输入被配置为从单元外部接收数据。 诸如第二多路复用器的输出元件被配置为接收字使能。 第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。

公开(公告)号：US5920097A

公开(公告)日：1999-07-06

申请号：US824323

申请日：1997-03-26

Applicant: Stephen C. Horne

Inventor： Stephen C. Horne

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/72

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A compact, integrated semiconductor device includes a first transistor and a second transistor. The first transistor has a gate formed by a first portion of a gate material. A second portion of the gate material provides the bulk material for a second transistor. The device can be utilized in a six-transistor SRAM cell. The two-transistor structure can include a p-channel transistor and an n-channel transistor of such a cell.

Abstract translation: 紧凑的集成半导体器件包括第一晶体管和第二晶体管。 第一晶体管具有由栅极材料的第一部分形成的栅极。 栅极材料的第二部分提供用于第二晶体管的体材料。 该器件可用于六晶体管SRAM单元。 双晶体管结构可以包括这种单元的p沟道晶体管和n沟道晶体管。

公开(公告)号：US06732346B2

公开(公告)日：2004-05-04

申请号：US10155042

申请日：2002-05-24

Applicant: Stephen C. Horne ,  Gopal Vijayan ,  Donald W. Glowka

Inventor： Stephen C. Horne ,  Gopal Vijayan ,  Donald W. Glowka

IPC: G06F1750

CPC classification number: G06F17/5077

Abstract: This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.

Abstract translation: 本发明公开了一种在半导体器件中的逻辑门之间产生线路规则的软件工具20，用于设备中的逻辑门的自动布局。 软件工具20包括路由规则生成工具22，其为给定的半导体制造技术和电路逻辑门系列创建路由规则数据库30，并且包括块逻辑门建立工具32，其将逻辑门与根据路由规则的路由互连 路由规则生成工具22还包括噪声敏感度/门表征工具24和规则生成器工具28.块构建工具32还包括门尺寸工具34，门分析工具36 ，路线规则选择工具38，路线分配工具42。

公开(公告)号：US06571378B1

公开(公告)日：2003-05-27

申请号：US09587729

申请日：2000-06-05

Applicant: James S. Blomgren ,  Terence M. Potter ,  Stephen C. Horne ,  Michael R. Seningen ,  Anthony M. Petro

Inventor： James S. Blomgren ,  Terence M. Potter ,  Stephen C. Horne ,  Michael R. Seningen ,  Anthony M. Petro

IPC: G06F1750

CPC classification number: G11C8/00 ,  G06F1/08 ,  G06F5/015 ,  G06F7/02 ,  G06F7/026 ,  G06F7/483 ,  G06F7/49 ,  G06F7/508 ,  G06F7/5443 ,  G06F17/5045 ,  G06F2207/3824 ,  G11C7/1006 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  H03K19/0002 ,  H03K19/00346 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/0813 ,  H03K19/0963 ,  H03K19/215

Abstract: A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Abstract translation: 公开了具有改善的电容隔离的逻辑器件和减小寄生电容的设计方法。 逻辑器件包括虚拟接地节点，可以是一个或多个N-NARY信号的单独线的多个输入信号以及两个或更多个放电路径。 每个放电路径包括评估节点，由输入信号选通的一个或多个晶体管，以及一个或多个中间节点，其中一个中间节点耦合到虚拟接地节点。 在一个实施例中，对于输入的每个组合，排出路径彼此完全隔离。 在另一个实施例中，放电路径上的中间节点可以仅在耦合到虚拟接地节点的中间节点处电耦合到评估路径。

公开(公告)号：US06412085B1

公开(公告)日：2002-06-25

申请号：US09468760

申请日：1999-12-21

Applicant: Stephen C. Horne ,  Kenneth D. Amstutz

Inventor： Stephen C. Horne ,  Kenneth D. Amstutz

IPC: G01R3128

CPC classification number: G01R31/318577 ,  G01R31/318594

Abstract: The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.

Abstract translation: 本发明是将N-NARY逻辑和动态逻辑初始化为特殊应力模式的方法和装置。 本发明具有包括具有一个或多个评估节点的共享逻辑树，一个或多个预充电装置和评估装置的逻辑电路。 耦合到评估节点的是产生状态信号的状态产生控制电路。 状态产生电路从状态产生控制电路接收状态信号，并将评估节点初始化为将逻辑电路初始化为特殊压力模式的功能非法状态。 本发明的一个实施例将评估节点初始化为低状态。 当一系列逻辑电路中的第一逻辑电路被初始化为功能非法状态时，本发明将在不同时钟域中的每个阶段评估系列中的后续逻辑电路的初始化，其将后续逻辑电路初始化为特殊 压力模式。

公开(公告)号：US06191034B1

公开(公告)日：2001-02-20

申请号：US09286401

申请日：1999-04-05

Applicant: Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

Inventor： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC: H01L2144

CPC classification number: H01L21/76892 ,  H01L21/32139

Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Abstract translation: 在导电线图案中形成最小间隙或空间的方法，用于通过首先在通过常规光学平版印刷在导电线上的绝缘层中形成开口，随后在开口中形成减小开口的侧壁，从而增加集成电路的密度， 并且使用所述侧壁作为掩模，优选地通过蚀刻除去所述导电线图案的大小与所述减小的开口大致相等的部分。

公开(公告)号：US5892373A

公开(公告)日：1999-04-06

申请号：US790393

申请日：1997-01-29

Applicant: Raghuram S. Tupuri ,  Stephen C. Horne

Inventor： Raghuram S. Tupuri ,  Stephen C. Horne

IPC: H03K3/037 ,  H03K19/096

CPC classification number: H03K3/0375

Abstract: A gated clock driver is configured to provide an enable signal and a gated clock signal at each of a plurality flip-flops. One of the p-channel transistors of the gated clock driver's NOR gate is distributed to each of the flip-flops or latches in the system. Additionally, an extra n-channel transistor is provided in the gated clock circuit to form an inverter with the nondistributed p-channel transistor. More particularly, the p-channel transistor that is driven by the system clock input is distributed to each of the flip-flops. Similarly, the enable input (at the output of the new inverter) is distributed to each of the flip-flops. Since the gated clock signal cannot be generated without the enable signal being high and the system clock being low, distributing enable and the p-channel transistor which receives the system clock as an input minimizes clock skew as compared to flip-flops with a completely shared clock gating clock.

Abstract translation: 门控时钟驱动器被配置为在多个触发器中的每一个提供使能信号和门控时钟信号。 门控时钟驱动器的或非门的p沟道晶体管之一被分配到系统中的每个触发器或锁存器。 此外，在门控时钟电路中提供了额外的n沟道晶体管，以形成具有非分布式p沟道晶体管的反相器。 更具体地，由系统时钟输入驱动的p沟道晶体管被分配到每个触发器。 类似地，使能输入（在新的反相器的输出处）被分配给每个触发器。 由于门控时钟信号不能在没有使能信号为高电平且系统时钟为低的情况下产生，所以与具有完全共享的触发器相比，接收系统时钟作为输入的分配使能和p沟道晶体管使时钟偏移最小化 时钟门控时钟。

公开(公告)号：US5844836A

公开(公告)日：1998-12-01

申请号：US822518

申请日：1997-03-24

Applicant: Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

Inventor： Nicholas John Kepler ,  Asim A. Selcuk ,  Richard K. Klein ,  Craig S. Sander ,  John C. Holst ,  Christopher A. Spence ,  Raymond T. Lee ,  Stephen C. Horne

IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104

Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Abstract translation: 在存储节点处具有增加的单元电容的静态随机存取存储器（SRAM）单元利用电容结构。 电容结构包括多晶硅导电线与钨局部互连之间的电介质材料。 多晶硅板各自连接到与SRAM单元相关联的横向晶体管的漏极。 可以在局部互连和多晶硅导电线之间沉积诸如二氧化硅的电介质材料。 电容器结构设置在与SRAM单元相关联的第一和第二N沟道下拉晶体管之间。

公开(公告)号：US5812832A

公开(公告)日：1998-09-22

申请号：US011068

申请日：1993-01-29

Applicant: Stephen C. Horne ,  Scott H. R. McMahon

Inventor： Stephen C. Horne ,  Scott H. R. McMahon

IPC: H03K5/151 ,  G06F1/04 ,  H03K5/156 ,  G06F1/08

CPC classification number: H03K5/1565 ,  G06F1/04

Abstract: A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than an externally applied clock signal. In one embodiment, the waveform generator includes a delay chain and a control unit that matches the propagation delay of the delay chain to the period of an input timing signal. The waveform generator provides precise control of the duty cycles of the internally generated clock signals, and allows for rapid starting and stopping of the internal clock signals for power reduction functions. The waveform generator may further provide a system clock, and may include circuitry to precisely control the phase relationships between the various clock signals. The waveform generator is easily manufactured with digital circuitry that automatically compensates for changing environmental conditions such as operating voltage and temperature.

Abstract translation: 提供了一种用于产生时钟信号的数字时钟波形发生器和方法，用于微处理器或其它数字电路，以提供具有与外部施加的时钟信号相同频率或更高或更低频率的内部时钟信号的片上产生。 在一个实施例中，波形发生器包括延迟链和控制单元，其将延迟链的传播延迟与输入定时信号的周期相匹配。 波形发生器可精确控制内部产生的时钟信号的占空比，并允许快速启动和停止用于功耗降低功能的内部时钟信号。 波形发生器还可以提供系统时钟，并且可以包括用于精确控制各种时钟信号之间的相位关系的电路。 波形发生器易于制造，数字电路可自动补偿不断变化的环境条件，如工作电压和温度。