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公开(公告)号：US20140075401A1
公开(公告)日：2014-03-13
申请号：US13609723
申请日：2012-09-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for the identification and implementation of a logic function includes determining logic gates connected to a control signal that is common among the logic gates of the identified logic function. Standard cells may be created and characterized in order to implement the identified logic function. Creating the standard cell includes aligning respective portions of the logic devices included in the logic gates that are coupled to the control signal. In addition, creating the standard cell may also include routing the control signal using a single layer conductive material uni-directionally to interconnect the logic devices.
摘要翻译： 用于识别和实现逻辑功能的方法包括确定连接到所识别的逻辑功能的逻辑门之间公用的控制信号的逻辑门。 可以创建和表征标准单元以便实现所识别的逻辑功能。 创建标准单元包括对齐与控制信号耦合的逻辑门中包括的逻辑器件的各部分。 此外，创建标准单元还可以包括使用单层导电材料单向地布线控制信号以互连逻辑器件。
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公开(公告)号：US08559249B1
公开(公告)日：2013-10-15
申请号：US13431424
申请日：2012-03-27
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
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公开(公告)号：US06911846B1
公开(公告)日：2005-06-28
申请号：US09019278
申请日：1998-02-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G11C8/10 , G11C11/56 , H03K19/003 , H03K19/096
CPC分类号： G11C11/56 , G11C7/1006 , G11C8/10 , H03K19/00346 , H03K19/0963
摘要： The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.
摘要翻译： 本发明包括一种用于集成电路（IC）的方法和装置，其使用N个信号中的1个来减少电路的导线以有效电容。 本发明包括一个逻辑树电路，其耦合到N个输入信号的第一个1，N个输入信号的第二个1和N个输出信号中的1个，其中N个信号的1个将信号的导线降低到有线电容。 本发明的其它实施例包括使用2个信号中的1个，3个信号中的1个，4个信号中的1个，以及信号中的一个和一个有效的8个信号中的1个信号。
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公开(公告)号：US06211456B1
公开(公告)日：2001-04-03
申请号：US09073479
申请日：1998-05-06
IPC分类号： H01B1104
CPC分类号： G06F1/08 , G06F17/5045 , G11C5/063 , G11C7/1006 , G11C8/10 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963
摘要： The present invention is a method and apparatus of routing a 1 of 4 signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a first, second, third, and fourth wire for routing a 1 of 4 signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire to be adjacent to each other wire for ½ of the wire's route.
摘要翻译： 本发明是一种方法和装置，用于对4个信号中的1个进行路由以减少信号线之间的有效信号耦合。 本发明是一种具有第一，第二，第三和第四电线的电线组件，用于在半导体器件中路由4个信号中的1个信号。 在布线电线的电线的同时，本发明旋转各个电线的路线，以减少电线之间的信号耦合。 此外，隔离屏障与电线组件的外部相邻，以进一步减少信号耦合。 电线的旋转允许每根单独的电线与电线的一半线路相邻。
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公开(公告)号：US6104642A
公开(公告)日：2000-08-15
申请号：US207806
申请日：1998-12-09
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , G11C7/00
CPC分类号： G06F7/5443 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.
摘要翻译： 本发明是一种用于存储信息的寄存器单元的方法和装置。 该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。 多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。 复用器还被配置为提供存储数据，第一输入被配置为从单元外部接收数据。 诸如第二多路复用器的输出元件被配置为接收字使能。 第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。
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公开(公告)号：US08947120B2
公开(公告)日：2015-02-03
申请号：US13613184
申请日：2012-09-13
IPC分类号： H03K19/173
CPC分类号： G06F17/5045
摘要： A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.
摘要翻译： 用于在集成电路上实现锁存阵列功能的电路。 包括在由公共信号控制的锁存阵列功能的实施中的逻辑设备的部分可以被排列成特定的对准。 单层单向导电材料可以将公共信号连接到逻辑器件。
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公开(公告)号：US20130265836A1
公开(公告)日：2013-10-10
申请号：US13443170
申请日：2012-04-10
CPC分类号： G11C7/08 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/12015 , G11C29/50
摘要： Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.
摘要翻译： 公开了可以允许弱数据存储单元的检测和补偿的存储器的实施例。 存储器可以包括数据存储单元，选择电路，读出放大器以及定时和控制块。 定时和控制块可操作以可控地选择激活选择电路和感测放大器的激活之间的不同时间段。
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公开(公告)号：US20130229877A1
公开(公告)日：2013-09-05
申请号：US13409399
申请日：2012-03-01
CPC分类号： G11C29/50 , G11C7/06 , G11C11/41 , G11C29/12 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。
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公开(公告)号：US20130223158A1
公开(公告)日：2013-08-29
申请号：US13403543
申请日：2012-02-23
CPC分类号： G11C29/50 , G11C11/41 , G11C29/52 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例。 存储器可以包括数据存储单元，列多路复用器，读出放大器和负载电路。 负载电路可以包括一个或多个容性负载，并且可操作以可控制地选择一个或多个容性负载以耦合到读出放大器的输入端。
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公开(公告)号：US20130049805A1
公开(公告)日：2013-02-28
申请号：US13215287
申请日：2011-08-23
IPC分类号： H03K19/02
CPC分类号： G11C11/412 , H03K19/00 , H03K19/0963
摘要： A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two.
摘要翻译： 一种用于N-Nary动态逻辑（NDL）电路的n位存储单元。 存储单元可以接受输入值并提供对应于输入值的补码输出值。 然而，如果接收到与预充电输入值对应的输入值，则输出值保持以前的输出值。 存储单元可以被实现为接受反相或非反相的一个n个NDL信号，并且分别提供N个大于2的非反相或反向的N个NDL信号作为输出。
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