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公开(公告)号：US08559249B1
公开(公告)日：2013-10-15
申请号：US13431424
申请日：2012-03-27
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
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公开(公告)号：US08780657B2
公开(公告)日：2014-07-15
申请号：US13409399
申请日：2012-03-01
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C7/06 , G11C11/41 , G11C29/12 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。
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公开(公告)号：US08780654B2
公开(公告)日：2014-07-15
申请号：US13443170
申请日：2012-04-10
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/12015 , G11C29/50
摘要： Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.
摘要翻译： 公开了可以允许弱数据存储单元的检测和补偿的存储器的实施例。 存储器可以包括数据存储单元，选择电路，读出放大器以及定时和控制块。 定时和控制块可操作以可控地选择激活选择电路和感测放大器的激活之间的不同时间段。
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公开(公告)号：US08555121B2
公开(公告)日：2013-10-08
申请号：US13026892
申请日：2011-02-14
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318541 , G01R31/318594
摘要： A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.
摘要翻译： 可扫描脉冲动态逻辑门可以包括评估网络，其评估响应于评估脉冲的断言的动态输入。 评估脉冲可以从时钟信号产生，使得其持续时间比时钟信号短。 在正常操作模式期间，当评估脉冲被断言时，评估网络可以根据动态输入的状态来放电动态节点。 然后动态节点可以驱动输出设备。 当评估脉冲无效时，可以对动态节点进行预充电。 门还可以包括扫描输入设备，其在扫描操作模式期间可以响应于扫描主时钟的断言将扫描输入数据加载到输出节点上。 响应于从属扫描时钟的断言，门的存储元件可以接收并捕获输出节点的值。
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公开(公告)号：US20130265836A1
公开(公告)日：2013-10-10
申请号：US13443170
申请日：2012-04-10
CPC分类号： G11C7/08 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/12015 , G11C29/50
摘要： Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.
摘要翻译： 公开了可以允许弱数据存储单元的检测和补偿的存储器的实施例。 存储器可以包括数据存储单元，选择电路，读出放大器以及定时和控制块。 定时和控制块可操作以可控地选择激活选择电路和感测放大器的激活之间的不同时间段。
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公开(公告)号：US20130229877A1
公开(公告)日：2013-09-05
申请号：US13409399
申请日：2012-03-01
CPC分类号： G11C29/50 , G11C7/06 , G11C11/41 , G11C29/12 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。
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公开(公告)号：US20130223158A1
公开(公告)日：2013-08-29
申请号：US13403543
申请日：2012-02-23
CPC分类号： G11C29/50 , G11C11/41 , G11C29/52 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例。 存储器可以包括数据存储单元，列多路复用器，读出放大器和负载电路。 负载电路可以包括一个或多个容性负载，并且可操作以可控制地选择一个或多个容性负载以耦合到读出放大器的输入端。
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公开(公告)号：US09177671B2
公开(公告)日：2015-11-03
申请号：US13403543
申请日：2012-02-23
CPC分类号： G11C29/50 , G11C11/41 , G11C29/52 , G11C2029/5002
摘要： A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
摘要翻译： 可能允许检测弱数据存储单元的存储器可以包括数据存储单元，列多路复用器，读出放大器和负载电路。 负载电路可以包括一个或多个容性负载，并且可操作以可控制地选择一个或多个容性负载以耦合到读出放大器的输入端。
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公开(公告)号：US08677199B2
公开(公告)日：2014-03-18
申请号：US13026878
申请日：2011-02-14
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318541 , G01R31/318594
摘要： A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The resultant state of the dynamic node may be stored within an output storage element. When the evaluate pulse is deasserted, the dynamic node may be precharged. During a scan mode of operation, the dynamic node may remain precharged. Scan data may be transferred to the output storage element under the control of scan-related control signals.
摘要翻译： 可扫描脉冲动态逻辑门可以包括评估网络，其评估响应于评估脉冲的断言的动态输入。 评估脉冲可以从时钟信号产生，使得其持续时间比时钟信号短。 在正常操作模式期间，当评估脉冲被断言时，评估网络可以根据动态输入的状态来放电动态节点。 动态节点的合成状态可以存储在输出存储元件内。 当评估脉冲无效时，可以对动态节点进行预充电。 在扫描操作模式期间，动态节点可以保持预充电。 扫描数据可以在扫描相关控制信号的控制下传送到输出存储元件。
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公开(公告)号：US08953395B2
公开(公告)日：2015-02-10
申请号：US13403564
申请日：2012-02-23
IPC分类号： G11C7/08
CPC分类号： G11C7/065 , G11C7/067 , G11C7/08 , G11C7/222 , G11C11/41 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/52 , G11C2029/5002 , G11C2207/002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a misread while reading a weak data storage cell. The memory column may include a number of data storage cells, a column multiplexer, and a sense amplifier. The sense amplifier may have two or more gain elements which can be individually selected to adjust the gain level of the sense amplifier.
摘要翻译： 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低误读的可能性。 存储器列可以包括多个数据存储单元，列多路复用器和读出放大器。 读出放大器可以具有两个或更多个增益元件，这些增益元件可被单独选择以调整读出放大器的增益电平。
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