This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.