公开(公告)号：US08859424B2

公开(公告)日：2014-10-14

申请号：US12840903

申请日：2010-07-21

Applicant: Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

Inventor： Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

IPC: H01L21/44 ,  H01L21/683

CPC classification number: H01L21/6833 ,  Y10T29/49124

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract translation: 公开了一种用于半导体晶片载体的系统和方法。 一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。 另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

公开(公告)号：US08501587B2

公开(公告)日：2013-08-06

申请号：US12613408

申请日：2009-11-05

Applicant: Ming-Fa Chen ,  Jao Sheng Huang

Inventor： Ming-Fa Chen ,  Jao Sheng Huang

IPC: H01L21/467 ,  H01L21/441

CPC classification number: H01L23/49816 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Abstract translation: 描述形成叠层半导体芯片的结构和方法。 在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。 开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。 第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。 抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。 蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

公开(公告)号：US20100178761A1

公开(公告)日：2010-07-15

申请号：US12613408

申请日：2009-11-05

Applicant: Ming-Fa Chen ,  Jao Sheng Huang

Inventor： Ming-Fa Chen ,  Jao Sheng Huang

IPC: H01L21/768

CPC classification number: H01L23/49816 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Abstract translation: 描述形成叠层半导体芯片的结构和方法。 在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。 开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。 第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。 抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。 蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

公开(公告)号：US08820728B2

公开(公告)日：2014-09-02

申请号：US12617851

申请日：2009-11-13

Applicant: Jao Sheng Huang ,  Ming-Fa Chen

Inventor： Jao Sheng Huang ,  Ming-Fa Chen

IPC: B23Q3/00

CPC classification number: H01L21/67346 ,  H01L21/67132

Abstract: A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.

Abstract translation: 公开了一种用于保护半导体晶片的系统和方法。 优选实施例包括具有中心区域和外部区域的载体。 外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。 优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。 半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

公开(公告)号：US20100194014A1

公开(公告)日：2010-08-05

申请号：US12617851

申请日：2009-11-13

Applicant: Jao Sheng Huang ,  Ming-Fa Chen

Inventor： Jao Sheng Huang ,  Ming-Fa Chen

IPC: H01L21/673 ,  B29C65/14

CPC classification number: H01L21/67346 ,  H01L21/67132

Abstract: A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.

Abstract translation: 公开了一种用于保护半导体晶片的系统和方法。 优选实施例包括具有中心区域和外部区域的载体。 外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。 优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。 半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

公开(公告)号：US20110035937A1

公开(公告)日：2011-02-17

申请号：US12840903

申请日：2010-07-21

Applicant: Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

Inventor： Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

IPC: H05K13/00

CPC classification number: H01L21/6833 ,  Y10T29/49124

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract translation: 公开了一种用于半导体晶片载体的系统和方法。 一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。 另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

公开(公告)号：US10297550B2

公开(公告)日：2019-05-21

申请号：US12774558

申请日：2010-05-05

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L23/488 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US08901736B2

公开(公告)日：2014-12-02

申请号：US12789696

申请日：2010-05-28

Applicant: Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

Inventor： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/35 ,  Y10T428/12361 ,  Y10T428/12396 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

Abstract translation: 一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。 金属凸块和电介质层部分的表面形成界面。 在金属凸块上方形成金属涂层并与金属凸块接触。 金属表面从介电层上延伸到界面的下方。

公开(公告)号：US08791549B2

公开(公告)日：2014-07-29

申请号：US12832019

申请日：2010-07-07

Applicant: Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

Inventor： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Abstract translation: 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US08546235B2

公开(公告)日：2013-10-01

申请号：US13101788

申请日：2011-05-05

Applicant: Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

Inventor： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

IPC: H01L21/20

CPC classification number: H01L28/40

Abstract: An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

Abstract translation: 集成电路包括衬底和设置在衬底上的第一金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括设置在基板上的第一金属电容器板。 至少一个第一绝缘体层设置在第一金属电容器板上。 第二金属电容器板设置在至少一个第一绝缘体层上。 至少一个第一电介质层设置在衬底上。 所述至少一个第一介电层的至少一部分设置在所述第一金属电容器板和所述至少一个第一绝缘体层之间。