公开(公告)号：US20240038633A1

公开(公告)日：2024-02-01

申请号：US17876376

申请日：2022-07-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Belgacem Haba ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L23/473 ,  H01L23/467 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/32

CPC classification number: H01L23/473 ,  H01L23/467 ,  H01L25/105 ,  H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L23/32 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2225/06517 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/05693 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2924/05432 ,  H01L2924/04642 ,  H01L2224/08245 ,  H01L2224/94 ,  H01L2224/80486 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

公开(公告)号：US20230036441A1

公开(公告)日：2023-02-02

申请号：US17816346

申请日：2022-07-29

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Belgacem Haba ,  Laura Wills Mirkarimi ,  Christopher Aubuchon ,  Rajesh Katkar

IPC: H01L23/00

Abstract: A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.

公开(公告)号：US20220293567A1

公开(公告)日：2022-09-15

申请号：US17681563

申请日：2022-02-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Thomas Workman ,  Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Gabriel Z. Guevara ,  Joy Watanabe

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

公开(公告)号：US20220246564A1

公开(公告)日：2022-08-04

申请号：US17681019

申请日：2022-02-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Liang Wang ,  Gaius Gillman Fountain, JR. ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20220155490A1

公开(公告)日：2022-05-19

申请号：US17587921

申请日：2022-01-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Belgacem Haba ,  Rajesh Katkar ,  Ilyas MOHAMMED

IPC: G02B1/10 ,  G02B1/02 ,  G02B27/01

Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.

公开(公告)号：US11296044B2

公开(公告)日：2022-04-05

申请号：US16553535

申请日：2019-08-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Guilian Gao ,  Javier A. Delacruz ,  Shaowu Huang ,  Liang Wang ,  Gaius Gillman Fountain, Jr. ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20220005784A1

公开(公告)日：2022-01-06

申请号：US17320767

申请日：2021-05-14

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Rajesh Katkar ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

公开(公告)号：US11205625B2

公开(公告)日：2021-12-21

申请号：US16846177

申请日：2020-04-10

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Javier A. DeLaCruz ,  Rajesh Katkar

IPC: H01L23/00

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

公开(公告)号：US20180174995A1

公开(公告)日：2018-06-21

申请号：US15387385

申请日：2016-12-21

Applicant: INVENSAS BONDING TECHNOLOGIES INC.

Inventor： Liang Wang ,  Rajesh Katkar ,  Javier A. DeLaCruz ,  Arkalgud R. Sitaram

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L24/29 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53242 ,  H01L2224/29019

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

公开(公告)号：US20230019869A1

公开(公告)日：2023-01-19

申请号：US17812675

申请日：2022-07-14

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Laura Wills Mirkarimi ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L23/498

Abstract: An optically occlusive protective element for bonded structures, embodiments of which disclosed herein relate to directly bonded structures along a bond interface. Specifically, two elements, a semiconductor element and an occlusive element, may be directly bonded to one another without an intervening adhesive along a bonding interface. The semiconductor element includes active circuitry which, after bonding, is protected by the occlusive element. The occlusive element includes several optically occlusive layers which are arranged to inhibit an optical interrogation of the active circuitry. Such layers may further include occlusive strips which may or may not overlap with other occlusive strips from other occlusive layers when the occlusive layers are stacked vertically.