Invention Grant
- Patent Title: Wafer-level bonding of obstructive elements
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Application No.: US16846177Application Date: 2020-04-10
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Publication No.: US11205625B2Publication Date: 2021-12-21
- Inventor: Javier A. DeLaCruz , Rajesh Katkar
- Applicant: INVENSAS BONDING TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
- Current Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
Public/Granted literature
- US20200328165A1 WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS Public/Granted day:2020-10-15
Information query
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