公开(公告)号：US12176268B2

公开(公告)日：2024-12-24

申请号：US16828405

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Digvijay Raorane ,  Sairam Agraharam ,  Nitin Deshpande ,  Mitul Modi ,  Manish Dubey ,  Edvin Cetegen

IPC: H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

公开(公告)号：US20240113088A1

公开(公告)日：2024-04-04

申请号：US17957926

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Harini Kilambi ,  Jagat Shakya ,  Debendra Mallik

IPC: H01L25/10 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L22/32 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83438 ,  H01L2224/83894

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.

公开(公告)号：US20230197547A1

公开(公告)日：2023-06-22

申请号：US17557945

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L24/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L21/56 ,  H01L2224/32145 ,  H01L2225/06517

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

公开(公告)号：US20200273772A1

公开(公告)日：2020-08-27

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US10438930B2

公开(公告)日：2019-10-08

申请号：US15639640

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Omkar Karhade ,  Christopher L. Rumer ,  Nitin Deshpande ,  Robert M. Nickerson

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/54 ,  H01L23/04 ,  H01L25/10

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

公开(公告)号：US09583470B2

公开(公告)日：2017-02-28

申请号：US14135209

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/488 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/1131 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16155 ,  H01L2224/16238 ,  H01L2224/8109 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3841 ,  H01L2924/00

Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.

Abstract translation: 示出了包括焊盘结构的电子设备和形成电互连的方法。 示出了包括从焊盘延伸的一个或多个突起的焊盘，其中突起仅占据焊盘表面积的一部分。 还示出了如所描述的使用焊盘的热压接的工艺。

公开(公告)号：US09576942B1

公开(公告)日：2017-02-21

申请号：US14974811

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/02 ,  H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

Abstract translation: 一种包括基板的集成电路组件; 形成在基板上的部件; 在所述构件中的开口内安装到所述基板的第一模具，使得在所述第一模具和所述构件之间存在空间，并且所述构件围绕所述第一模具，并且其中所述第一模具不在所述构件的上表面上方延伸; 第一模具和衬底之间的底部填充物，其中底部填充物至少部分地填充模具和构件之间的空间; 以及安装到所述第一模具和所述构件的第二模具，其中所述第二模具安装到所述开口的所有侧面上的所述构件。

公开(公告)号：US12044888B2

公开(公告)日：2024-07-23

申请号：US17131654

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Xiaoqian Li ,  Nitin Deshpande ,  Sujit Sharan

IPC: G02B6/42

CPC classification number: G02B6/4243 ,  G02B6/423 ,  G02B6/4239

Abstract: A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

公开(公告)号：US20230317680A1

公开(公告)日：2023-10-05

申请号：US17707340

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Prabhat Ranjan ,  Boon Ping Koh ,  Min Suet Lim ,  Yew San Lim ,  Ranjul Balakrishnan ,  Omkar Karhade ,  Robert A. Stingel ,  Nitin Deshpande

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/49 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2224/49176 ,  H01L2224/48097 ,  H01L2224/85986

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.