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1.发明公开公开(公告)号：US20240113088A1
公开(公告)日：2024-04-04
申请号：US17957926
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Omkar Karhade , Nitin Deshpande , Harini Kilambi , Jagat Shakya , Debendra Mallik
CPC classification number: H01L25/105 , H01L22/32 , H01L23/3157 , H01L24/08 , H01L24/80 , H01L24/83 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2224/83438 , H01L2224/83894
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.
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公开(公告)号：US12163982B2
公开(公告)日：2024-12-10
申请号：US17709487
申请日：2022-03-31
Applicant: Intel Corporation
Inventor： Jagat Shakya , Ethan Caughey , Joseph Parks, Jr.
Abstract: The present disclosure is directed to an inspection tool having a probe head with a probe card with a plurality of probes for performing testing, each of the probes being configured with a first end attached to the probe card and a second end for engaging microbumps coupled to a semiconductor die, the plurality of probes including a first set of probes having a first cross-sectional dimension, the first set of probes being arranged in a first set of locations on the probe card, and a second set of probes having a second cross-sectional dimension, the second set of probes being arranged in a second set of locations on the probe card, and a stage for holding the semiconductor die.
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3.发明授权公开(公告)号：US11740282B1
公开(公告)日：2023-08-29
申请号：US17709483
申请日：2022-03-31
Applicant: Intel Corporation
Inventor： Jagat Shakya , Joseph Parks, Jr. , Ethan Caughey , Ashwin Ashok , Prasanna Thiyagasundaram
CPC classification number: G01R31/2891 , G01R1/0483 , G01R1/07314 , G01R31/2853 , G01R31/2886 , G01R31/2887 , H01L2924/00 , H01L2924/01006 , H01L2924/01033
Abstract: An apparatus includes an input probe configured to be placed on a first cluster of u-bumps disposed on a semiconductor die, output probes configured to be respectively placed on multiple clusters of u-bumps disposed on the semiconductor die, the multiple clusters being separately connected to the first cluster. The apparatus further includes a space transformer and printed circuit board (PCB) portion including a current source configured to supply a current to the input probe placed on the first cluster, resistors having a same resistance and being connected to ground, and tester channels at which voltages are respectively measured, the tester channels being respectively connected to ends of the output probes respectively placed on the multiple clusters and being respectively connected to the resistors. The apparatus further includes a processor configured to determine whether the input probe is properly aligned with the first cluster, based on the measured voltages.
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公开(公告)号：US11527501B1
公开(公告)日：2022-12-13
申请号：US17122934
申请日：2020-12-15
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Veronica Aleman Strong , Shawna M. Liff , Brandon M. Rawlings , Jagat Shakya , Johanna M. Swan , David M. Craig , Jeremy Alan Streifer , Brennen Karl Mueller
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.
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Patent Agency Ranking
公开(公告)号：US20240413031A1
公开(公告)日：2024-12-12
申请号：US18207808
申请日：2023-06-09
Applicant: Intel Corporation
Inventor： Chandru Periasamy , Jagat Shakya , Joshua Jeremy Cardiel Rivera , Jaime A. Sanchez , Devesh Srivastava , Feras Eid , Matthew Zeman , Xavier F. Brun , Nabankur Deb
IPC: H01L23/31 , H01L21/56 , H01L23/367 , H01L23/373
Abstract: An electronic device and associated methods are disclosed. Electronic devices are shown that include a semiconductor die and a patterned layer connected to a backside of the die. Electronic devices are shown that include a pattern of elements across a patterned layer that varies across the backside of a die. Electronic devices are further shown that include a compliant filler within elements in a patterned layer.
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公开(公告)号：US11749628B2
公开(公告)日：2023-09-05
申请号：US18053869
申请日：2022-11-09
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Veronica Aleman Strong , Shawna M. Lift , Brandon M. Rawlings , Jagat Shakya , Johanna M. Swan , David M. Craig , Jeremy Alan Streifer , Brennen Karl Mueller
CPC classification number: H01L24/06 , B81B7/0006 , B81B7/007
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.
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公开(公告)号：US20230074970A1
公开(公告)日：2023-03-09
申请号：US18053869
申请日：2022-11-09
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Veronica Aleman Strong , Shawna M. Liff , Brandon M. Rawlings , Jagat Shakya , Johanna M. Swan , David M. Craig , Jeremy Alan Streifer , Brennen Karl Mueller
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.
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公开(公告)号：US11486923B2
公开(公告)日：2022-11-01
申请号：US16210259
申请日：2018-12-05
Applicant: Intel Corporation
Inventor： Jagat Shakya , Ethan Caughey , Jeremy Alan Streifer
Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.
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公开(公告)号：US20200182928A1
公开(公告)日：2020-06-11
申请号：US16210259
申请日：2018-12-05
Applicant: Intel Corporation
Inventor： Jagat Shakya , Ethan Caughey , Jeremy Alan Streifer
Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.
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