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    Non-volatile semiconductor memory device
    1.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5553026A

    公开(公告)日：1996-09-03

    申请号：US364348

    申请日：1994-12-27

    申请人： Hiroto Nakai ,  Tadashi Miyakawa ,  Shigeru Matsuda

    发明人： Hiroto Nakai ,  Tadashi Miyakawa ,  Shigeru Matsuda

    IPC分类号： G11C16/06 ,  G11C16/02 ,  G11C16/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/26 ,  G11C29/34 ,  G11C7/00

    CPC分类号： G11C29/34 ,  G11C16/16 ,  G11C29/26

    摘要： The non-volatile memory device comprises a memory cell array, a block decoder, and a decode signal reading section. The memory cell array has a plurality of cell blocks. Each of the cell blocks is composed of a plurality of memory cells arranged roughly into a matrix pattern. Each memory cell has a floating gate to or from which electrons are injected or extracted to write or erase data. The block decoder receives a block address, and outputs a decode signal to select a cell block corresponding to the block address from the cell blocks. The memory cells of the selected block are erased simultaneously. When a control signal is inputted to the block decoder, the block decoder outputs the decode signal to select all the cell blocks for erasure of the memory cells of all the cell blocks simultaneously, irrespective of the block address. The decode signal reading section outputs the decode signal to the outside. The decode signal is applied to the cell blocks and in parallel to the decode signal reading section itself and further outputted to the outside therethrough. In the memory device, the block erase function can be checked at a short time and additionally the other functional blocks can be checked simply.

    摘要翻译： 非易失性存储器件包括存储单元阵列，块解码器和解码信号读取部分。 存储单元阵列具有多个单元块。 每个单元块由大致排列成矩阵图案的多个存储单元构成。 每个存储单元都有一个浮动栅极，从其中注入或提取电子以写入或擦除数据。 块解码器接收块地址，并且输出解码信号以从单元块中选择与块地址相对应的单元块。 所选块的存储单元同时被擦除。 当控制信号被输入到块解码器时，块解码器输出解码信号以选择用于擦除所有单元块的存储单元的所有单元块，而与块地址无关。 解码信号读取部将解码信号输出到外部。 解码信号被施加到单元块并且与解码信号读取部分本身并行地进一步输出到外部。 在存储器件中，可以在短时间内检查块擦除功能，另外可以简单地检查其他功能块。

    Semiconductor device and memory protection method
    2.
    发明授权
    Semiconductor device and memory protection method 有权
    半导体器件和存储器保护方法

    公开(公告)号：US08892810B2

    公开(公告)日：2014-11-18

    申请号：US13399185

    申请日：2012-02-17

    申请人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

    发明人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

    IPC分类号： G06F12/02 ,  G06F9/54

    CPC分类号： G06F9/524 ,  G06F9/544 ,  G06F12/0246

    摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

    摘要翻译： 根据一个实施例，半导体器件包括处理器和存储器件。 存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。 当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系 在存储器件中，用于各个工作台。 处理器参考相应工作台的相应表访问存储器件。

    Resistance change memory device
    3.
    发明授权
    Resistance change memory device 有权
    电阻变化记忆装置

    公开(公告)号：US08400816B2

    公开(公告)日：2013-03-19

    申请号：US13237500

    申请日：2011-09-20

    申请人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

    发明人： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

    摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

    摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

    Integrated memory management and memory management method
    4.
    发明授权
    Integrated memory management and memory management method 有权
    集成内存管理和内存管理方法

    公开(公告)号：US08135900B2

    公开(公告)日：2012-03-13

    申请号：US12236880

    申请日：2008-09-24

    申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

    发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda

    IPC分类号： G06F12/10 ,  G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7211

    摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

    摘要翻译： 根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址， 来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及 传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

    Semiconductor memory device with dual reference elements
    8.
    发明授权
    Semiconductor memory device with dual reference elements 失效
    具有双参考元件的半导体存储器件

    公开(公告)号：US5197028A

    公开(公告)日：1993-03-23

    申请号：US568034

    申请日：1990-08-16

    申请人： Hiroto Nakai

    发明人： Hiroto Nakai

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28

    CPC分类号： G11C16/28

    摘要： The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of a first reference cell to receive a first reference cell data. A second reference cell has a drain, a gate and a source. A second reference line is connected to the drain of the second reference cell for receiving a second reference cell data. A gate voltage generating circuit having an output node is connected to the gate of the first reference cell for controlling the gate potential of the first reference cell so that the potentials at the first and second reference lines have the same power source voltage dependancy. A data detecting circuit reads the memory cell data in accordance with the comparison result between the potentials.

    摘要翻译： 本发明涉及具有具有漏极，栅极和源极的存储单元的半导体存储器件。 存储单元的栅极被提供有用于读取存储单元数据的第一电位。 第一参考线连接到第一参考单元的漏极以接收第一参考单元数据。 第二参考单元具有漏极，栅极和源极。 第二参考线连接到第二参考单元的漏极，用于接收第二参考单元数据。 具有输出节点的栅极电压产生电路连接到第一参考单元的栅极，用于控制第一参考单元的栅极电位，使得第一和第二参考线上的电位具有相同的电源电压依赖性。 数据检测电路根据电位之间的比较结果读取存储单元数据。

    Voltage detecting circuit
    10.
    发明授权
    Voltage detecting circuit 失效
    电压检测电路

    公开(公告)号：US4922133A

    公开(公告)日：1990-05-01

    申请号：US226097

    申请日：1988-07-29

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Masamichi Asano

    IPC分类号： H01L21/8247 ,  G11C16/06 ,  G11C17/00 ,  H01L21/822 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H03K5/08 ,  H03K17/30

    CPC分类号： H03K17/302 ,  H03K5/08

    摘要： A voltage detecting circuit comprising a voltage-input terminal for receiving a first voltage or a second voltage higher than the first voltage, switch means connected between the voltage-input terminal and a first node, and an inverter circuit having an input terminal coupled to the first node and an output terminal coupled to a second node. The switch circuit is turned on when the voltage at the voltage-input terminal is higher than a predetermined value which is between the higher than the first voltage and lower than the second voltage, and is turned off when the voltage at the voltage-input terminal is lower than the predetermined value. The inverter circuit includes a first transistor having a source-drain path coupled between a first power-source potential terminal and the second node, a current control section for maintaining a current flowing through the source-drain path of the first transistor at a predetermined value, and a second transistor having a source-drain path connected between the second node and a second power-source potential terminal and a gate coupled to the first node.

    摘要翻译： 一种电压检测电路，包括用于接收高于第一电压的第一电压或第二电压的电压输入端子，连接在电压输入端子和第一节点之间的开关装置，以及具有耦合到第一电压的输入端子的反相器电路 第一节点和耦合到第二节点的输出终端。 当电压输入端子的电压高于高于第一电压且低于第二电压的预定值时，开关电路导通，并且当电压输入端子处的电压 低于预定值。 逆变器电路包括：第一晶体管，其具有耦合在第一电源电位端子和第二节点之间的源极 - 漏极路径;电流控制部分，用于将流过第一晶体管的源极 - 漏极通路的电流保持在预定值 以及第二晶体管，其源极 - 漏极路径连接在第二节点和第二电源电位端子之间，栅极耦合到第一节点。