公开(公告)号：US07319614B2

公开(公告)日：2008-01-15

申请号：US11414631

申请日：2006-04-27

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the thresheld voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均化，以减少它们的保持电压的分散。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任一个存储在存储单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US20060193173A1

公开(公告)日：2006-08-31

申请号：US11414631

申请日：2006-04-27

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage in allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减少来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储单元组或块的存储单元中，分配给用于存储更多位侧的存储单元的负阈值电压 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06785166B2

公开(公告)日：2004-08-31

申请号：US10414344

申请日：2003-04-16

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，将负阈值电压分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06549462B1

公开(公告)日：2003-04-15

申请号：US09699632

申请日：2000-10-31

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

公开(公告)号：US06301158B1

公开(公告)日：2001-10-09

申请号：US09079912

申请日：1998-05-15

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C1606

CPC分类号： G11C16/0491 ,  G11C16/08

摘要： A virtual grounded type EEPROM including a memory cell array includes a plurality of memory cells arranged in a matrix. A control gates of the memory cells of the same row are connected to one of word lines. The adjacent two memory cells of the same row are connected such that a drain of one of them is connected to a source of the other. The source and drain of the adjacent two memory cells are connected to one of bit lines. A row decoder selects one of the word lines and a column decoder selects one of the bit lines. A program circuit applies a high voltage to the drain of a selected memory cell. The row decoder determines whether a high voltage should be applied to the selected word line. The row decoder also determines whether or not to permit the charge storage layer to store charges. The data programming is executed such that data programming for the memory cells of one column is completed first and then data programming for the memory cells of an adjacent column is started, and such that data programming makes progress from the memory cells at one end of each memory cell array to the memory cells at the other end of the memory cell array.

摘要翻译： 包括存储单元阵列的虚拟接地型EEPROM包括以矩阵形式排列的多个存储单元。 同一行的存储单元的控制栅极连接到一行字线。 相同行的相邻两个存储单元被连接，使得其中一个的漏极连接到另一个的源极。 相邻两个存储单元的源极和漏极连接到位线之一。 行解码器选择一个字线，并且列解码器选择一个位线。 一个程序电路向所选存储单元的漏极施加高电压。 行解码器确定是否应该对所选择的字线施加高电压。 行解码器还确定是否允许电荷存储层存储电荷。 执行数据编程，使得首先完成一列的存储单元的数据编程，然后开始相邻列的存储单元的数据编程，并且使得数据编程从每个存储单元的一端处的存储器单元进行 存储单元阵列到存储单元阵列另一端的存储单元。

公开(公告)号：US6081453A

公开(公告)日：2000-06-27

申请号：US59949

申请日：1998-04-14

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L29/78

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/30

摘要： A nonvolatile semiconductor memory device includes a memory cell having a drain electrically connected to a bit line, a source, a floating gate, and a control gate electrically connected to a word line, a sense amplifier for comparing a plurality of predetermined reference voltages with the bit line voltage to detect data stored in the memory cell and outputting one of first, second, and third outputs, and a logic circuit for determining stored data of two bits on the basis of the logic calculation of the first, second, and third outputs. It is determined whether desired data has been written, based on data read out in a verify-read operation after a write operation, at a time later than that for outputting readout data in a read operation. With this arrangement, the difference in read rate between selected memory cells can be minimized.

摘要翻译： 非易失性半导体存储器件包括具有电连接到位线的漏极，电连接到字线的源极，浮动栅极和控制栅极的存储单元，用于将多个预定参考电压与 位线电压以检测存储在存储单元中的数据并输出第一，第二和第三输出之一;以及逻辑电路，用于基于第一，第二和第三输出的逻辑运算来确定两位的存储数据 。 基于在写入操作之后的验证读取操作中读出的数据，比在读取操作中输出读出数据的时间晚，确定是否写入了所需数据。 利用这种布置，可以使选择的存储单元之间的读取速率差异最小化。

公开(公告)号：US5808939A

公开(公告)日：1998-09-15

申请号：US694404

申请日：1996-08-12

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of "0" or "1" of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任一个存储在存储单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US5745413A

公开(公告)日：1998-04-28

申请号：US731914

申请日：1996-10-22

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C11/40

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuits. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 串联电路在一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

公开(公告)号：US5557570A

公开(公告)日：1996-09-17

申请号：US449750

申请日：1995-05-25

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/26 ,  G11C16/344

摘要： Memory cells are arrange in the row and column directions in the form of a matrix. A transistor as a load is connected to column lines. A sense amplifier is connected to the transistor. In a read check operation, in which the data in the memory cells are erased, and the erased state of each memory cell is checked, all the row lines are set in a non-selected state by a row decoder, and all the column lines are selected by a column decoder. In this state the sum of currents flowing in the memory cells is detected by the sense amplifier. When the current detected by the sense amplifier becomes a predetermined value, a data erase operation is ended.

摘要翻译： 存储单元以矩阵的形式排列在行和列方向上。 作为负载的晶体管连接到列线。 感测放大器连接到晶体管。 在检查存储单元中的数据被擦除并且检查每个存储单元的擦除状态的读取检查操作中，行解码器将所有行线设置为非选择状态，并且所有列线 由列解码器选择。 在这种状态下，读出放大器检测在存储单元中流动的电流之和。 当由读出放大器检测到的电流变为预定值时，数据擦除操作结束。

公开(公告)号：US5022002A

公开(公告)日：1991-06-04

申请号：US218403

申请日：1988-07-13

申请人： Hiroshi Iwahashi

发明人： Hiroshi Iwahashi

IPC分类号： G11C17/00 ,  G11C5/06 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

CPC分类号： G11C5/147 ,  G11C16/30 ,  G11C5/066

摘要： A programmable ROM is made up of a power source terminal, an internal power source voltage generator, a memory cell array, a memory cell drive circuit, and a data read-out circuit. The power source terminal receives a power source voltage of 5 V in a read mode, and a power source voltage of 12.5 V in a program mode. The internal power source voltage generator generates an internal power source voltage substantially equal to or lower than 5 V, on the basis of the power source voltage applied to the power source terminal. The memory cell array contains a plurality of memory cells. Each of the memory cells is a MOS transistor with the floating gate structure. The memory cell drive circuit is connected to the power source terminal and the internal power source voltage generator, for receiving a drive power source. The data read-out circuit is connected to the internal power source voltage generator, for receiving a drive power source. The memory drive circuit supplies a read-out voltage of 5 V to the memory cells in a read mode, and a program voltage of 12.5 V in a program mode. The data read-out circuit is driven by the 5 V power source voltage, and reads out data from the memory cells in a read mode.

摘要翻译： 可编程ROM由电源端子，内部电源电压发生器，存储单元阵列，存储单元驱动电路和数据读出电路组成。 电源端子在读取模式下接收5V电源电压，在程序模式下接收电源电压12.5V。 内部电源电压发生器基于施加到电源端子的电源电压产生基本上等于或低于5V的内部电源电压。 存储单元阵列包含多个存储单元。 每个存储单元是具有浮动栅极结构的MOS晶体管。 存储单元驱动电路连接到电源端子和内部电源电压发生器，用于接收驱动电源。 数据读出电路连接到内部电源电压发生器，用于接收驱动电源。 存储器驱动电路在读取模式下向存储器单元提供5V的读出电压，并且在编程模式下提供12.5V的编程电压。 数据读出电路由5 V电源电压驱动，并以读取模式从存储单元读出数据。