公开(公告)号：US20130248975A1

公开(公告)日：2013-09-26

申请号：US13607702

申请日：2012-09-08

申请人： Tomoo HISHIDA ,  Yoshihisa Iwata

发明人： Tomoo HISHIDA ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/53266 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-volatile semiconductor memory device includes a peripheral circuit having multilayer wirings. Above this peripheral circuit, a plurality of memory strings is formed. The memory strings include a plurality of memory cells and a back gate transistor connected in series. Multiple back gate layers are formed to function as a control electrode of the back gate transistor. A first connection part composed of semiconductor films connects a lower surface of one of the back gate layers and an upper surface of the uppermost wiring layer of the multilayer wirings, and a barrier metal film is disposed above the uppermost wiring layer.

摘要翻译： 非易失性半导体存储器件包括具有多层布线的外围电路。 在该外围电路上方形成多个存储器串。 存储器串包括串联连接的多个存储单元和背栅晶体管。 多个背栅层被形成为用作背栅晶体管的控制电极。 由半导体膜构成的第一连接部分将背栅层之一的下表面和多层布线的最上布线层的上表面连接，并且阻挡金属膜设置在最上布线层的上方。

公开(公告)号：US20130003433A1

公开(公告)日：2013-01-03

申请号：US13423546

申请日：2012-03-19

申请人： Tomoo HISHIDA ,  Yoshihisa IWATA

发明人： Tomoo HISHIDA ,  Yoshihisa IWATA

IPC分类号： G11C5/02

CPC分类号： H01L27/11582 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/10 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US08315097B2

公开(公告)日：2012-11-20

申请号：US13026616

申请日：2011-02-14

申请人： Tomoo Hishida ,  Hitoshi Iwai ,  Yoshihisa Iwata

发明人： Tomoo Hishida ,  Hitoshi Iwai ,  Yoshihisa Iwata

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  H01L27/11582

摘要： A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.

摘要翻译： 存储器串由多个存储晶体管和备用存储晶体管串联连接。 字线连接到存储晶体管的栅极。 备用字线连接到备用存储晶体管的栅极。 存储器串包括第一半导体层，电荷存储层，多个第一导电层和第二导电层。 第一半导体层相对于基板在垂直方向上延伸。 电荷存储层包围第一半导体层的侧表面。 多个第一导电层围绕第一半导体层的侧表面，电荷存储层位于其间，并用作字线。 第二导电层围绕第一半导体层的侧表面，电荷存储层位于其间，用作备用字线。

公开(公告)号：US20120069655A1

公开(公告)日：2012-03-22

申请号：US13026616

申请日：2011-02-14

申请人： Tomoo Hishida ,  Hitoshi Iwai ,  Yoshihisa Iwata

发明人： Tomoo Hishida ,  Hitoshi Iwai ,  Yoshihisa Iwata

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/11582

摘要： A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.

摘要翻译： 存储器串由多个存储晶体管和备用存储晶体管串联连接。 字线连接到存储晶体管的栅极。 备用字线连接到备用存储晶体管的栅极。 存储器串包括第一半导体层，电荷存储层，多个第一导电层和第二导电层。 第一半导体层相对于基板在垂直方向上延伸。 电荷存储层包围第一半导体层的侧表面。 多个第一导电层围绕第一半导体层的侧表面，电荷存储层位于其间，并用作字线。 第二导电层围绕第一半导体层的侧表面，电荷存储层位于其间，用作备用字线。

公开(公告)号：US20120068256A1

公开(公告)日：2012-03-22

申请号：US13232492

申请日：2011-09-14

申请人： Ryo Fukuda ,  Yoshihisa Iwata

发明人： Ryo Fukuda ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0416 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

摘要翻译： 在半导体衬底上方形成绝缘膜。 第一导电层形成在电介质膜中并沿第一方向延伸。 第一导电层连接到第一选择晶体管。 形成在电介质膜中并沿第一方向延伸的第二导电层。 第二导电层连接到第二选择晶体管。 半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。 在半导体层上形成栅极绝缘膜。 栅极绝缘膜包括作为其一部分的电荷累积膜。 第三导电层被栅极绝缘膜包围。

公开(公告)号：US20120043601A1

公开(公告)日：2012-02-23

申请号：US13275436

申请日：2011-10-18

申请人： Takashi MAEDA ,  Yoshihisa Iwata

发明人： Takashi MAEDA ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

摘要翻译： 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

公开(公告)号：US20110175159A1

公开(公告)日：2011-07-21

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US07933151B2

公开(公告)日：2011-04-26

申请号：US12564576

申请日：2009-09-22

申请人： Takashi Maeda ,  Yoshihisa Iwata

发明人： Takashi Maeda ,  Yoshihisa Iwata

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C5/02 ,  G11C7/18 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

摘要： Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

摘要翻译： 存储器串包括：第一半导体层，包括沿垂直于衬底的方向延伸的柱状部分; 形成为围绕所述柱状部的侧面的第一电荷存储层; 以及形成为围绕所述第一电荷存储层的第一导电层。 第一选择晶体管包括：从柱状部分的顶表面向上延伸的第二半导体层; 形成为包围第二半导体层的侧面的第二电荷存储层; 以及形成为围绕所述第二电荷存储层的第二导电层。 非易失性半导体存储装置还包括控制电路，其在从所选择的一个存储器串中读取数据之前，将电荷累积在连接到第一选择晶体管的第一选择晶体管的第二电荷存储层中 取消选择一个内存字符串。

公开(公告)号：US20110013454A1

公开(公告)日：2011-01-20

申请号：US12726858

申请日：2010-03-18

申请人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhel Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhel Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  G11C16/0483 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

摘要翻译： 非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。 开关电路控制第二线和第一线之间的电连接。

公开(公告)号：US20100238732A1

公开(公告)日：2010-09-23

申请号：US12718353

申请日：2010-03-05

申请人： Tomoo HISHIDA ,  Yoshihisa Iwata

发明人： Tomoo HISHIDA ,  Yoshihisa Iwata

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.

摘要翻译： 当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。 在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。 然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。 然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。 将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。 其他第一导电层进入浮置状态。