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公开(公告)号：US10396740B2
公开(公告)日：2019-08-27
申请号：US15684625
申请日：2017-08-23
Inventor： Yi-Gyeong Kim , Woo Seok Yang , Min-Hyung Cho
Abstract: The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise.
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公开(公告)号：US20250067841A1
公开(公告)日：2025-02-27
申请号：US18733086
申请日：2024-06-04
Inventor： Yi-Gyeong KIM , Kyung Hwan Park , Sujin Park , Young-deuk Jeon , Min-Hyung Cho
Abstract: Disclosed is an ultra-wide band (UWB) radar device including a first antenna circuit including a first transmission circuit, a first reception circuit, a first oscillator that supplies a first clock signal to the first transmission circuit and the first reception circuit, and a first frequency counter, a second antenna circuit including a second transmission circuit, a second reception circuit, a second oscillator that supplies a second clock signal to the second transmission circuit and the second reception circuit, and a second frequency counter, and a controller that detects the target. The controller corrects a frequency error between the first clock signal and the second clock signal and compensates for a synchronization error between the first antenna circuit and the second antenna circuit.
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公开(公告)号：US11695411B2
公开(公告)日：2023-07-04
申请号：US17484375
申请日：2021-09-24
Inventor： Min-Hyung Cho , Young-deuk Jeon , In San Jeon , Jin Ho Han
IPC: H04B1/04 , H03K17/56 , H03K5/01 , H04L1/00 , H03K19/20 , H03K19/018 , H03K19/00 , H03K19/0185 , H03K19/0175 , H03K5/00
CPC classification number: H03K17/56 , H03K5/01 , H03K19/0005 , H03K19/01825 , H03K19/017545 , H03K19/018557 , H03K19/20 , H04L1/0009 , H04L1/0033 , H03K2005/00013
Abstract: Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.
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公开(公告)号：US11494630B2
公开(公告)日：2022-11-08
申请号：US16742808
申请日：2020-01-14
Inventor： Young-deuk Jeon , Byung Jo Kim , Ju-Yeob Kim , Jin Kyu Kim , Ki Hyuk Park , Mi Young Lee , Joo Hyun Lee , Min-Hyung Cho
Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.
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公开(公告)号：US12266400B2
公开(公告)日：2025-04-01
申请号：US17983016
申请日：2022-11-08
Inventor： Min-Hyung Cho , Young-Deuk Jeon , Jin Ho Han
IPC: G11C11/4099 , G11C5/04 , G11C5/06
Abstract: A method for ZQ calibration for a data transmission driving circuit of each memory die in a memory chip package in which memory dies are stacked, includes generating a reference current through a reference resistor connected between a power terminal supplying a power voltage of the data transmission driving circuit and a ground terminal and a first transistor that is diode-connected; supplying first currents corresponding to the reference currents to a pull-up driver of each memory die; performing ZQ calibration of a pull-up driver of a corresponding memory die by comparing a first voltage formed by each first current with a reference voltage formed by the reference current in each of the plurality of memory dies; and performing ZQ calibration of a pull-down driver of the corresponding memory die based on an output impedance of the ZQ calibrated pull-up driver in each of the memory dies.
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Patent Agency Ranking
公开(公告)号：US12206420B2
公开(公告)日：2025-01-21
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong Kim , Young-Su Kwon , Su-Jin Park , Young-Deuk Jeon , Min-Hyung Cho , Jae-Woong Choi
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US12087392B2
公开(公告)日：2024-09-10
申请号：US17565937
申请日：2021-12-30
Inventor： Young-Deuk Jeon , Min-Hyung Cho , Young-Su Kwon , Jin Ho Han
CPC classification number: G11C7/1084 , G11C7/1057 , G11C7/225 , G11C8/18
Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
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公开(公告)号：US11449720B2
公开(公告)日：2022-09-20
申请号：US16870412
申请日：2020-05-08
Inventor： Ju-Yeob Kim , Byung Jo Kim , Seong Min Kim , Jin Kyu Kim , Ki Hyuk Park , Mi Young Lee , Joo Hyun Lee , Young-deuk Jeon , Min-Hyung Cho
IPC: G06K9/62
Abstract: Provided is an image recognition device. The image recognition device includes a frame data change detector that sequentially receives a plurality of frame data and detects a difference between two consecutive frame data, an ensemble section controller that sets an ensemble section in the plurality of frame data, based on the detected difference, an image recognizer that sequentially identifies classes respectively corresponding to a plurality of section frame data by applying different neural network classifiers to the plurality of section frame data in the ensemble section, and a recognition result classifier that sequentially identifies ensemble classes respectively corresponding to the plurality of section frame data by combining the classes in the ensemble section.
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9.发明授权Current-voltage conversion amplifier circuit including multiplier with a current offset removal unit and multi input amplifier 有权电流 - 电压转换放大器电路包括具有电流偏移去除单元和多输入放大器的乘法器公开(公告)号：US09543907B2
公开(公告)日：2017-01-10
申请号：US14605877
申请日：2015-01-26
Inventor： Young-deuk Jeon , Jung Hee Suk , Chun-Gi Lyuh , Yi-Gyeong Kim , Jong Pil Im , Min-Hyung Cho
CPC classification number: H03F3/082 , H03F3/087 , H03F3/45475 , H03F2203/45088 , H03F2203/45514 , H03F2203/45551 , H03F2203/45614 , H03G3/008 , H03M1/121
Abstract: Provided is a current-voltage conversion amplifier circuit including: a plurality of light receiving devices generating a current signal proportional to an amount of light by receiving the light; multipliers amplifying the current signal, converting the amplified current signal into a first voltage signal, outputting the amplified current signal, or outputting the converted first voltage signal; multi input amplifiers outputting first and second output voltage pairs through a process for receiving output values of multipliers and an offset voltage and amplifying the received output values and offset voltage; a multiplexing unit selecting and outputting one first and second output voltage pair among the first and second output voltage pairs outputted from multi input amplifiers; and a signal conversion unit converting a difference value between first and second output voltages outputted from the multiplexing unit and outputting the converted digital signal.
Abstract translation: 提供了一种电流 - 电压转换放大器电路，包括：多个光接收装置，通过接收光产生与光量成比例的电流信号; 放大电流信号的乘法器，将放大的电流信号转换成第一电压信号，输出放大的电流信号或输出转换的第一电压信号; 多输入放大器，通过用于接收乘法器的输出值和偏移电压的过程输出第一和第二输出电压对，并放大所接收的输出值和失调电压; 多路复用单元，从多输入放大器输出的第一和第二输出电压对中选择并输出一个第一和第二输出电压对; 以及信号转换单元，转换从多路复用单元输出的第一和第二输出电压之间的差值，并输出转换的数字信号。
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公开(公告)号：US20150131813A1
公开(公告)日：2015-05-14
申请号：US14304156
申请日：2014-06-13
Inventor： Yi-Gyeong KIM , Min-Hyung Cho , Young-deuk JEON , Tae Moon ROH , Woo Seok YANG , Jong-Kee KWON
CPC classification number: H03F1/0266 , H03F3/211 , H03F2200/411 , H04R3/08
Abstract: Provided is a capacitor-type sensor read-out circuit. The capacitor-type sensor read-out circuit includes: a signal conversion unit outputting a sensor signal inputted from a sensor; a voltage booster generating a bias voltage; and a capacitor-type signal coupling circuit receiving the sensor signal as a feedback, mixing the received sensor signal with the bias voltage, and outputting the mixed signal.
Abstract translation: 提供了一种电容式传感器读出电路。 电容式传感器读出电路包括：信号转换单元，输出从传感器输入的传感器信号; 产生偏置电压的升压器; 接收传感器信号作为反馈的电容器型信号耦合电路，将接收到的传感器信号与偏置电压进行混合，并输出混合信号。
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