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    MULTI-CORE PROCESSOR AND OPERATION METHOD THEREOF
    1.
    发明申请
    MULTI-CORE PROCESSOR AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20180165246A1

    公开(公告)日：2018-06-14

    申请号：US15832824

    申请日：2017-12-06

    申请人： Electronics and Telecommunications Research Institute

    发明人： Jin Ho Han ,  Kyoung Seon Shin ,  Young-Su Kwon

    IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F12/0842 ,  G06F11/07

    摘要： A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.

    Semiconductor system including fault manager
    3.
    发明授权
    Semiconductor system including fault manager 有权

    公开(公告)号：US11036595B2

    公开(公告)日：2021-06-15

    申请号：US16117403

    申请日：2018-08-30

    申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    发明人： Jin Ho Han ,  Min-Seok Choi ,  Young-Su Kwon

    IPC分类号： G06F11/14 ,  G06F11/07

    摘要： Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.

    Multi-core processor and cache management method thereof
    4.
    发明授权
    Multi-core processor and cache management method thereof 有权

    公开(公告)号：US10740167B2

    公开(公告)日：2020-08-11

    申请号：US15832862

    申请日：2017-12-06

    申请人： Electronics and Telecommunications Research Institute

    发明人： Jin Ho Han ,  Young-Su Kwon

    IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0868 ,  G06F11/16

    摘要： A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.

    Cache control device having fault-tolerant function and method of operating the same
    5.
    发明授权
    Cache control device having fault-tolerant function and method of operating the same 有权
    具有容错功能的高速缓存控制装置及其操作方法

    公开(公告)号：US09575692B2

    公开(公告)日：2017-02-21

    申请号：US14690843

    申请日：2015-04-20

    申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    发明人： Jin Ho Han ,  Young Su Kwon

    IPC分类号： G11C29/00 ,  G06F3/06 ,  G06F11/10

    CPC分类号： G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1064

    摘要： The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

    摘要翻译： 具有容错功能的高速缓存控制装置包括高速缓存存储器，被配置为存储关于从主存储器读取的特定地址的第一数据，并且生成并存储对应于第一数据的第一奇偶校验位， 存储关于特定地址的第二数据，并且生成并存储与第二数据相对应的第二奇偶校验位;以及故障检测器，被配置为对存储在其中的特定地址和奇偶校验位的数据执行奇偶校验操作 当从处理器接收关于特定地址的数据读取请求时，缓存存储器和影子高速缓存存储器中的至少一个，并且根据奇偶校验操作的结果将存储在非错误存储器中的数据发送到处理器 。

    Cache with scratch pad memory structure and processor including the cache
    6.
    发明授权
    Cache with scratch pad memory structure and processor including the cache 有权
    缓存与临时存储器结构和处理器包括缓存

    公开(公告)号：US08954676B2

    公开(公告)日：2015-02-10

    申请号：US13680243

    申请日：2012-11-19

    申请人： Electronics and Telecommunications Research Institute

    发明人： Jin Ho Han

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0875 ,  G06F12/0802 ,  G06F12/084 ,  G06F2212/6012 ,  Y02D10/13

    摘要： Disclosed are a cache with a scratch pad memory (SPM) structure and a processor including the same. The cache with a scratch pad memory structure includes: a block memory configured to include at least one block area in which instruction codes read from an external memory are stored; a tag memory configured to store an external memory address corresponding to indexes of the instruction codes stored in the block memory; and a tag controller configured to process a request from a fetch unit for the instruction codes, wherein a part of the block areas is set as a SPM area according to cache setting input from a cache setting unit. According to the present invention, it is possible to reduce the time to read instruction codes from the external memory and realize power saving by operating the cache as the scratch pad memory.

    摘要翻译： 公开了具有便笺式存储器（SPM）结构的高速缓冲存储器和包括其的处理器。 具有暂存器存储器结构的高速缓存包括：块存储器，被配置为包括存储从外部存储器读取的指令代码的至少一个块区域; 标签存储器，被配置为存储对应于存储在块存储器中的指令代码的索引的外部存储器地址; 以及标签控制器，被配置为处理来自所述指令代码的取出单元的请求，其中，根据从高速缓存设置单元输入的高速缓存设置，将所述块区域的一部分设置为SPM区域。 根据本发明，可以减少从外部存储器读取指令代码的时间，并且通过操作高速缓存作为临时存储器来实现功率节省。