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公开(公告)号：US11036595B2
公开(公告)日：2021-06-15
申请号：US16117403
申请日：2018-08-30
发明人： Jin Ho Han , Min-Seok Choi , Young-Su Kwon
摘要： Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.
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2.发明授权公开(公告)号：US11176395B2
公开(公告)日：2021-11-16
申请号：US16694899
申请日：2019-11-25
发明人： Jin Ho Han , Young-Su Kwon , Yong Cheol Peter Cho , Min-Seok Choi
摘要： Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores arranged in rows and columns and configured to perform a pattern recognition operation on an input feature using a kernel coefficient in response to each instruction, an instruction memory configured to provide the instruction to each of the plurality of nano cores, a feature memory configured to provide the input feature to each of the plurality of nano cores, a kernel memory configured to provide the kernel coefficients to the plurality of nano cores, and a functional safety processor core configured to receive a result of a pattern recognition operation outputted from the plurality of nano cores to detect the presence of a recognition error, and perform a fault tolerance function on the detected recognition error.
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公开(公告)号：US11341066B2
公开(公告)日：2022-05-24
申请号：US17119387
申请日：2020-12-11
发明人： Jin Ho Han , Min-Seok Choi , Young-Su Kwon
IPC分类号： G06F13/16 , G06F12/02 , G06F12/1081 , G06F13/28
摘要： Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
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公开(公告)号：US10983878B2
公开(公告)日：2021-04-20
申请号：US16694913
申请日：2019-11-25
发明人： Jin Ho Han , Young-Su Kwon , Min-Seok Choi
摘要： Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.
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