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公开(公告)号:US11695411B2
公开(公告)日:2023-07-04
申请号:US17484375
申请日:2021-09-24
Inventor: Min-Hyung Cho , Young-deuk Jeon , In San Jeon , Jin Ho Han
IPC: H04B1/04 , H03K17/56 , H03K5/01 , H04L1/00 , H03K19/20 , H03K19/018 , H03K19/00 , H03K19/0185 , H03K19/0175 , H03K5/00
CPC classification number: H03K17/56 , H03K5/01 , H03K19/0005 , H03K19/01825 , H03K19/017545 , H03K19/018557 , H03K19/20 , H04L1/0009 , H04L1/0033 , H03K2005/00013
Abstract: Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.
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公开(公告)号:US11146253B1
公开(公告)日:2021-10-12
申请号:US17105817
申请日:2020-11-27
Inventor: Young-deuk Jeon , Young-Su Kwon , Seong Min Kim , In San Jeon , Min-Hyung Cho , Jin Ho Han
IPC: H03K3/00 , H03K3/3565 , H03K19/0185 , H03K19/00 , H03K5/08 , G11C11/413 , G01R19/165
Abstract: Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.
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公开(公告)号:US10361727B2
公开(公告)日:2019-07-23
申请号:US15360925
申请日:2016-11-23
Inventor: In San Jeon , Hyuk Kim
Abstract: Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first parities by performing a first error correction encoding on each of the input words, an interleaver for generating interleaved words by performing interleaving on the input words, a second encoder for generating a plurality of second parities by performing a second error correction encoding on each of the interleaved words, output nodes for outputting each of the input words, first parity output nodes for outputting the first parities, and second parity output nodes for outputting the second parities.
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