公开(公告)号：US09824017B2

公开(公告)日：2017-11-21

申请号：US14253349

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho Han ,  Young Su Kwon ,  Kyoung Seon Shin

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F12/0833

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

公开(公告)号：US09575692B2

公开(公告)日：2017-02-21

申请号：US14690843

申请日：2015-04-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho Han ,  Young Su Kwon

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1064

Abstract: The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

Abstract translation: 具有容错功能的高速缓存控制装置包括高速缓存存储器，被配置为存储关于从主存储器读取的特定地址的第一数据，并且生成并存储对应于第一数据的第一奇偶校验位， 存储关于特定地址的第二数据，并且生成并存储与第二数据相对应的第二奇偶校验位;以及故障检测器，被配置为对存储在其中的特定地址和奇偶校验位的数据执行奇偶校验操作 当从处理器接收关于特定地址的数据读取请求时，缓存存储器和影子高速缓存存储器中的至少一个，并且根据奇偶校验操作的结果将存储在非错误存储器中的数据发送到处理器 。

公开(公告)号：US09529654B2

公开(公告)日：2016-12-27

申请号：US14547301

申请日：2014-11-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young Su Kwon ,  Jin Ho Han ,  Kyung Jin Byun

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/18

CPC classification number: G06F11/0772 ,  G06F11/0721 ,  G06F11/183

Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。

公开(公告)号：US09501311B2

公开(公告)日：2016-11-22

申请号：US14602857

申请日：2015-01-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Jin Lee ,  Young Su Kwon

IPC: G06F9/46 ,  G06F9/455

CPC classification number: G06F9/461 ,  G06F9/455

Abstract: Provided are an apparatus and method for multicore emulation based on dynamic context switching. The apparatus for multicore emulation based on dynamic context switching includes a multicore emulation managing unit configured to transmit a signal for requesting determination of a core to be emulated among a plurality of cores, and a context switching managing unit configured to receive the signal for requesting determination of a core to be emulated from the multicore emulation managing unit, determine an ID of a core to be emulated according to the received signal, and executing emulation on a core corresponding to the determined core ID.

Abstract translation: 提供了一种基于动态上下文切换的多核仿真的装置和方法。 基于动态上下文切换的多核心仿真装置包括：多核仿真管理单元，被配置为发送用于请求确定要在多个核心中仿真的核心的信号;以及上下文切换管理单元，被配置为接收用于请求确定的信号 要从多核仿真管理单元仿真的核心，根据接收到的信号确定要仿真的核心的ID，以及对与所确定的核心ID相对应的核心执行仿真。