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    Fully parallel fast fourier transformer
    4.
    发明授权
    Fully parallel fast fourier transformer 有权

    公开(公告)号：US09735996B2

    公开(公告)日：2017-08-15

    申请号：US15348771

    申请日：2016-11-10

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jin Kyu Kim

    IPC: G06F17/14 ,  H04L27/26 ,  G06F9/30

    CPC classification number: H04L27/265 ,  G06F9/3001 ,  G06F17/141 ,  G06F17/142

    Abstract: Provided is a fully parallel fast Fourier transformer of N-point, where N is a natural number, including a bit-reversal arranging block configured to rearrange an order of N input complex number samples, a plurality of first processors configured to perform, in a plurality of group units, a 16-point FFT on the rearranged complex number samples, a twiddle factor multiplier configured to multiply outputs of the plurality of first processors by twiddle factors, a first group rearranging block configured to rearrange outputs of the twiddle factor multiplier in the plurality of group units, a plurality of second processors configured to perform, in the plurality of group units, 16-point FFT on the complex number samples grouped by the first group rearranging block, and a second group rearranging block configured to rearrange outputs of the plurality of second processors to output under a same arrangement criterion as the first group rearranging block.

    Quantization method and device for weights of batch normalization layer
    5.
    发明授权
    Quantization method and device for weights of batch normalization layer 有权

    公开(公告)号：US11455539B2

    公开(公告)日：2022-09-27

    申请号：US16541275

    申请日：2019-08-15

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Mi Young Lee ,  Byung Jo Kim ,  Seong Min Kim ,  Ju-Yeob Kim ,  Jin Kyu Kim ,  Joo Hyun Lee

    IPC: G06N3/08 ,  G06F17/18

    Abstract: An embodiment of the present invention provides a quantization method for weights of a plurality of batch normalization layers, including: receiving a plurality of previously learned first weights of the plurality of batch normalization layers; obtaining first distribution information of the plurality of first weights; performing a first quantization on the plurality of first weights using the first distribution information to obtain a plurality of second weights; obtaining second distribution information of the plurality of second weights; and performing a second quantization on the plurality of second weights using the second distribution information to obtain a plurality of final weights, and thereby reducing an error that may occur when quantizing the weight of the batch normalization layer.

    Neuromorphic arithmetic device and operating method thereof
    8.
    发明授权
    Neuromorphic arithmetic device and operating method thereof 有权

    公开(公告)号：US11494630B2

    公开(公告)日：2022-11-08

    申请号：US16742808

    申请日：2020-01-14

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-deuk Jeon ,  Byung Jo Kim ,  Ju-Yeob Kim ,  Jin Kyu Kim ,  Ki Hyuk Park ,  Mi Young Lee ,  Joo Hyun Lee ,  Min-Hyung Cho

    IPC: G06N3/063 ,  G06F7/575 ,  G06F17/15

    Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

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