Semiconductor apparatus, pixel circuit and control method thereof

    公开(公告)号:US11475833B2

    公开(公告)日:2022-10-18

    申请号:US16767351

    申请日:2019-12-18

    摘要: The present application discloses a semiconductor apparatus, a pixel circuit and a control method thereof. The semiconductor apparatus comprises: an active layer; a first insulating layer; a first gate and a second gate overlapping with a portion of the active layer with the first insulating layer interposed therebetween, respectively; a first electrode, a second electrode and a third electrode, the first electrode and the second electrode are electrically connected with a first portion and a second portion of the active layer, respectively, the third electrode is used to be electrically connected with a photosensitive device, wherein the third electrode is electrically connected with the first gate or the second gate; or the third electrode is electrically connected with a third portion of the active layer.

    Array substrate, display apparatus, and method of fabricating array substrate

    公开(公告)号:US11469261B2

    公开(公告)日:2022-10-11

    申请号:US16769725

    申请日:2019-08-20

    摘要: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.

    ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE

    公开(公告)号:US20210408088A1

    公开(公告)日:2021-12-30

    申请号:US16769725

    申请日:2019-08-20

    摘要: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.

    CHIP ON FILM, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

    公开(公告)号:US20240363510A1

    公开(公告)日:2024-10-31

    申请号:US18580229

    申请日:2022-11-24

    IPC分类号: H01L23/498 H01L21/48

    摘要: A chip on film includes: a flexible substrate; and a multilayer wiring structure disposed on the flexible substrate. The multilayer wiring structure includes a first wiring layer, a first insulation layer and a second wiring layer, which are sequentially arranged in a direction towards the flexible substrate the flexible substrate. The first wiring layer includes a first conductive material and the second wiring layer includes a second conductive material. The chip on film further includes: pins, at least part of which are in the first wiring layer; first via holes in the first insulation layer; and a second wire and a second wire leading portion in the second wiring layer, which are electrically connected to each other. More than one pin is electrically connected to the second wire leading portion through more than one first via hole, respectively.