公开(公告)号：US20230115986A1

公开(公告)日：2023-04-13

申请号：US18046134

申请日：2022-10-12

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC分类号： H01L23/00

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US09754924B2

公开(公告)日：2017-09-05

申请号：US15164296

申请日：2016-05-25

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

摘要： Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

公开(公告)号：US09601464B2

公开(公告)日：2017-03-21

申请号：US14328127

申请日：2014-07-10

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/552 ,  H01L21/48 ,  H01L23/36 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L21/4889 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/552 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81

摘要： In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include a first package, a second package, and a shield. The first package may include a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface substantially opposite the third surface, and a second die. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The shield may be applied to the fourth surface of the semiconductor device package assembly. In some embodiments, the shield may transfer, during use, heat from the first die.

公开(公告)号：US08766424B2

公开(公告)日：2014-07-01

申请号：US14013244

申请日：2013-08-29

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/315 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

摘要： A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

摘要翻译： PoP（封装封装）封装包括底部封装，其具有封装在具有与基板顶部耦合的管芯的密封剂中的基板。 裸片的至少一部分暴露在底部封装衬底上的密封剂上方。 顶部封装包括在衬底的前侧和后侧上具有密封剂的衬底。 顶部封装衬底的背面耦合到底部封装衬底的顶侧，其中模具的至少一部分位于封装材料的位于顶部封装衬底背面的凹槽中。

公开(公告)号：US11908819B2

公开(公告)日：2024-02-20

申请号：US18046134

申请日：2022-10-12

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L24/25 ,  H01L24/26 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14517 ,  H01L2224/16112 ,  H01L2224/24996 ,  H01L2224/2501 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/83051

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US20200381383A1

公开(公告)日：2020-12-03

申请号：US16423931

申请日：2019-05-28

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC分类号： H01L23/00

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US09379097B2

公开(公告)日：2016-06-28

申请号：US14494253

申请日：2014-09-23

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

摘要： Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

摘要翻译： 描述包装结构和形成方式。 在一个实施例中，沟槽阵列部分地通过扇出基板形成。 在一个实施例中，多个横向分开的位置热界面材料被分配到嵌入式底模的阵列上。 在一个实施例中，包括对应于顶部封装阵列的空腔阵列的热压缩工具在PoP接头形成期间与顶部封装阵列和下面的扇出基板接触。 在几个处理操作期间，扇出基板可以固定到真空卡盘。

公开(公告)号：US20150255366A1

公开(公告)日：2015-09-10

申请号：US14199400

申请日：2014-03-06

申请人： Apple Inc.

发明人： Chih-Ming Chung

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/3142 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： In some embodiments, a system and/or method may include forming a semiconductor device package assembly. The method may include forming a substrate including a first surface and a second surface substantially opposite the first surface. The substrate may include an opening in the second surface. The first surface may include a first set of electrical conductors. The method may include positioning a first die in the opening. The first die may include a second set of electrical conductors. The method may include forming a third set of electrical conductors on a second die. The third set of conductors may include a first width and a first height. The method may include forming a fourth set of electrical conductors on the second die. The fourth set of conductors may include a second width and a second height. The second width may be less than the first width. The second height may be greater than the first height.

摘要翻译： 在一些实施例中，系统和/或方法可以包括形成半导体器件封装组件。 该方法可以包括形成包括基本上与第一表面相对的第一表面和第二表面的基底。 衬底可以包括第二表面中的开口。 第一表面可以包括第一组电导体。 该方法可以包括将第一模具定位在开口中。 第一管芯可以包括第二组电导体。 该方法可以包括在第二管芯上形成第三组电导体。 第三组导体可以包括第一宽度和第一高度。 该方法可以包括在第二管芯上形成第四组电导体。 第四组导体可以包括第二宽度和第二高度。 第二宽度可以小于第一宽度。 第二高度可以大于第一高度。

公开(公告)号：US11545455B2

公开(公告)日：2023-01-03

申请号：US16423931

申请日：2019-05-28

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC分类号： H01L23/00

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US09583472B2

公开(公告)日：2017-02-28

申请号：US14637109

申请日：2015-03-03

申请人： Apple Inc.

发明人： Chih-Ming Chung ,  Jun Zhai ,  Yizhang Yang

IPC分类号： H01L25/18 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/34 ,  H01L23/552 ,  H01L25/16

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/14 ,  H01L24/19 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81

摘要： Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

摘要翻译： 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL），第一和第二RDL之间的堆叠管芯，以及在RDL之间延伸的导电柱。 模塑料可以将堆叠的管芯和导电柱塞在第一和第二RDL之间。