公开(公告)号：US20160268236A1

公开(公告)日：2016-09-15

申请号：US15164296

申请日：2016-05-25

Applicant: Apple Inc.

Inventor： Chih-Ming Chung

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

公开(公告)号：US20230399492A1

公开(公告)日：2023-12-14

申请号：US18456970

申请日：2023-08-28

Applicant: FUJIFILM Corporation

Inventor： Junji KAWAGUCHI

IPC: C08K5/3415 ,  H01L23/00 ,  C08L33/20

CPC classification number: C08K5/3415 ,  H01L24/26 ,  C08L33/20 ,  H01L2224/26

Abstract: An object of the present invention is to provide an underfill composition having excellent temporal stability and good metal adhesiveness, a coating film formed of the underfill composition, a cured film, a multilayer interconnection board, and a manufacturing method of a multilayer interconnection board. The underfill composition of the present invention is an underfill composition containing a polymer and a maleimide compound having a maleimide group, in which the polymer has a cyano group, and a content of the cyano group included in 1 g of the polymer is 0.1 to 6 mmol/g.

公开(公告)号：US20180219003A1

公开(公告)日：2018-08-02

申请号：US15325383

申请日：2016-02-03

Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

Inventor： Kosuke IKEDA

IPC: H01L25/07 ,  H01L25/18

CPC classification number: H01L25/071 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/26 ,  H01L2924/13055

Abstract: A semiconductor device has a first board (10) having a first electrically conducting layer (11) and a first electronic element (12) that is provided on the first electrically conducting layer (11); and an intermediate layer (20) being provided on the first board (10), and having a plurality of connectors and a resin board section, in which the plurality of connectors are fixed. The connector is exposed from the resin board section on the first board (10) side, and connected with the first electrically conducting layer (11) or the first electronic element (12).

公开(公告)号：US12002733B2

公开(公告)日：2024-06-04

申请号：US17983561

申请日：2022-11-09

Applicant: Lenovo (Singapore) Pte. Ltd.

Inventor： Masahiro Kitamura ,  Takuroh Kamimura ,  Junki Hashiba ,  Takateru Adachi

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/42 ,  H05K1/02

CPC classification number: H01L23/3736 ,  H01L23/367 ,  H01L23/42 ,  H05K1/0203 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26 ,  H01L2224/26125 ,  H01L2224/29105 ,  H01L2224/32245 ,  H01L2224/83447

Abstract: A heat dissipation structure of an electric component that generates heat includes: a heat dissipator provided along a surface of the electric component; a liquid metal interposed between the electric component and the heat dissipator; and a fencing body interposed between the electric component and the heat dissipator in a crushed state and surrounding the liquid metal.

公开(公告)号：US20160027766A1

公开(公告)日：2016-01-28

申请号：US14494253

申请日：2014-09-23

Applicant: Apple Inc.

Inventor： Chih-Ming Chung

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

Abstract translation: 描述包装结构和形成方式。 在一个实施例中，沟槽阵列部分地通过扇出基板形成。 在一个实施例中，多个横向分开的位置热界面材料被分配到嵌入式底模的阵列上。 在一个实施例中，包括对应于顶部封装阵列的空腔阵列的热压缩工具在PoP接头形成期间与顶部封装阵列和下面的扇出基板接触。 在几个处理操作期间，扇出基板可以固定到真空卡盘。

公开(公告)号：US09754924B2

公开(公告)日：2017-09-05

申请号：US15164296

申请日：2016-05-25

Applicant: Apple Inc.

Inventor： Chih-Ming Chung

IPC: H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

公开(公告)号：US08901724B2

公开(公告)日：2014-12-02

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L23/02 ,  H01L23/12 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L21/683 ,  H01L23/538 ,  H05K1/18 ,  H01L25/10 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US20110215464A1

公开(公告)日：2011-09-08

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L25/07 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US09780054B2

公开(公告)日：2017-10-03

申请号：US14529881

申请日：2014-10-31

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H01L21/768 ,  H01L25/07 ,  H01L23/31 ,  H01L25/11 ,  H05K3/46

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

公开(公告)号：US09379097B2

公开(公告)日：2016-06-28

申请号：US14494253

申请日：2014-09-23

Applicant: Apple Inc.

Inventor： Chih-Ming Chung

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/32225 ,  H01L2224/40108 ,  H01L2224/41171 ,  H01L2224/48108 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73151 ,  H01L2224/73267 ,  H01L2224/751 ,  H01L2224/753 ,  H01L2224/7555 ,  H01L2224/75981 ,  H01L2224/81203 ,  H01L2224/8136 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2224/26

Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

Abstract translation: 描述包装结构和形成方式。 在一个实施例中，沟槽阵列部分地通过扇出基板形成。 在一个实施例中，多个横向分开的位置热界面材料被分配到嵌入式底模的阵列上。 在一个实施例中，包括对应于顶部封装阵列的空腔阵列的热压缩工具在PoP接头形成期间与顶部封装阵列和下面的扇出基板接触。 在几个处理操作期间，扇出基板可以固定到真空卡盘。