公开(公告)号：US20140167275A1

公开(公告)日：2014-06-19

申请号：US13846807

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Sang Yong LEE ,  Si Han KIM

IPC: H01L23/49 ,  H01L23/00

CPC classification number: H01L24/03 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92132 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/185 ,  H05K3/12 ,  H05K3/18 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity.When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.

Abstract translation: 嵌入式封装，其中诸如半导体芯片的有源元件嵌入在封装衬底内。 嵌入在介电层内的半导体芯片与电路线耦合以确保电气和信号的连续性。 当在不同的方向上进行半导体芯片和封装基板之间的连接时，总的互连面积减小，连接可靠性提高，泄漏电流降低，并且可以实现更高的器件产量。

公开(公告)号：US20120248579A1

公开(公告)日：2012-10-04

申请号：US13238705

申请日：2011-09-21

Applicant: Mitsuyoshi ENDO

Inventor： Mitsuyoshi ENDO

IPC: H01L29/41 ,  H01L21/30

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

公开(公告)号：US09099313B2

公开(公告)日：2015-08-04

申请号：US13846807

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Sang Yong Lee ,  Si Han Kim

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/46

CPC classification number: H01L24/03 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92132 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/185 ,  H05K3/12 ,  H05K3/18 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.

Abstract translation: 嵌入式封装，其中诸如半导体芯片的有源元件嵌入在封装衬底内。 嵌入在介电层内的半导体芯片与电路线耦合以确保电气和信号的连续性。 当在不同的方向上进行半导体芯片和封装基板之间的连接时，总的互连面积减小，连接可靠性提高，泄漏电流降低，并且可以实现更高的器件产量。

公开(公告)号：US08901724B2

公开(公告)日：2014-12-02

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L23/02 ,  H01L23/12 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L21/683 ,  H01L23/538 ,  H05K1/18 ,  H01L25/10 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US08884396B2

公开(公告)日：2014-11-11

申请号：US13238705

申请日：2011-09-21

Applicant: Mitsuyoshi Endo

Inventor： Mitsuyoshi Endo

IPC: H01L23/52 ,  H01L21/768 ,  H01L25/065 ,  H01L21/683 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

Abstract translation: 根据一个实施例，将第一基板的第一后表面和第二基板的第二前表面接合在一起，以将第一导体与第二导体连接。 第一导体包括直径等于在第一金属层和第一前表面之间的范围内形成在第一金属层之上的第一间隙的直径的部分和具有大于第一间隙的直径的部分， 在第一金属层和第一背面之间的范围内小于第一金属层的外径。 第一绝缘层具有形成在第一金属层上方的间隙，该间隙大于第一间隙并小于第一金属层的外径。

公开(公告)号：US20110215464A1

公开(公告)日：2011-09-08

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L25/07 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US09780054B2

公开(公告)日：2017-10-03

申请号：US14529881

申请日：2014-10-31

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H01L21/768 ,  H01L25/07 ,  H01L23/31 ,  H01L25/11 ,  H05K3/46

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

公开(公告)号：US20150050781A1

公开(公告)日：2015-02-19

申请号：US14529881

申请日：2014-10-31

Applicant: John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US20120248624A1

公开(公告)日：2012-10-04

申请号：US13308826

申请日：2011-12-01

Applicant: Mitsuyoshi Endo

Inventor： Mitsuyoshi Endo

IPC: H01L23/48 ,  H01L21/302

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

Abstract translation: 根据一个实施例，将第一基板的第一后表面和第二基板的第二前表面接合在一起，以将第一导体与第二导体连接。 第一导体包括直径等于在第一金属层和第一前表面之间的范围内形成在第一金属层之上的第一间隙的直径的部分和具有大于第一间隙的直径的部分， 在第一金属层和第一背面之间的范围内小于第一金属层的外径。 第一绝缘层具有形成在第一金属层上方的间隙，该间隙大于第一间隙并小于第一金属层的外径。