公开(公告)号：US20120248579A1

公开(公告)日：2012-10-04

申请号：US13238705

申请日：2011-09-21

Applicant: Mitsuyoshi ENDO

Inventor： Mitsuyoshi ENDO

IPC: H01L29/41 ,  H01L21/30

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

公开(公告)号：US20130049210A1

公开(公告)日：2013-02-28

申请号：US13365516

申请日：2012-02-03

Applicant: Mitsuyoshi ENDO

Inventor： Mitsuyoshi ENDO

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L21/76256 ,  H01L24/08 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/056 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/05442 ,  H01L2924/049 ,  H01L2924/05042

Abstract: According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.

Abstract translation: 根据一个实施例，半导体晶片包括形成在半导体衬底上的半导体衬底和互连层。 在半导体晶片中，半导体衬底包括位于半导体衬底的外周侧并且未被互连层覆盖的第一区域。 互连层包括互连层的上表面基本上平坦的第二区域。 在第一区域形成第一绝缘膜。 第二区域内的互连层的上表面和第一绝缘膜的上表面基本上彼此齐平。

公开(公告)号：US20130168832A1

公开(公告)日：2013-07-04

申请号：US13606724

申请日：2012-09-07

Applicant: Mitsuyoshi ENDO

Inventor： Mitsuyoshi ENDO

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: According to one embodiment, a semiconductor device is provided such that a penetrating via with a conductive material embedded through a medium of an insulating film is formed in a through hole of a p-type semiconductor substrate. The semiconductor device includes an n-type well on an upper section of the p-type semiconductor substrate in the vicinity of the penetrating via, an electrode connected to the n-type well, and the electrode connected to the p-type semiconductor substrate in the vicinity of the electrode.

Abstract translation: 根据一个实施例，提供半导体器件，使得在p型半导体衬底的通孔中形成具有通过绝缘膜的介质嵌入的导电材料的穿透通孔。 半导体器件包括位于穿透通孔附近的p型半导体衬底的上部的n型阱，与n型阱连接的电极以及与p型半导体衬底连接的电极 电极附近。