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    PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES
    3.
    发明申请
    PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES 有权
    非易失性存储器件中的可编程峰值电流控制

    公开(公告)号：US20150098272A1

    公开(公告)日：2015-04-09

    申请号：US14322102

    申请日：2014-07-02

    Applicant: Apple Inc.

    Inventor： Yoav Kasorla ,  Avraham Poza Meir

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3422

    Abstract: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.

    Abstract translation: 一种方法包括在存储器装置中接收指定存储器件不被超出的峰值功率消耗的命令。 存储器件的存储器根据命令中指定的峰值功耗进行配置。 在配置的存储器中执行数据存储操作，同时符合规定的峰值功耗。

    POWER SHUTDOWN PREDICTION FOR NON-VOLATILE STORAGE DEVICES
    4.
    发明申请
    POWER SHUTDOWN PREDICTION FOR NON-VOLATILE STORAGE DEVICES 审中-公开
    用于非易失存储器件的电源关断预测

    公开(公告)号：US20150082099A1

    公开(公告)日：2015-03-19

    申请号：US14548489

    申请日：2014-11-20

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Shai Ojalvo ,  Moshe Neerman

    IPC: G06F11/30

    CPC classification number: G06F11/3058 ,  G06F1/26 ,  G06F1/30 ,  G06F9/4401 ,  G06F11/1441 ,  G06F11/3034

    Abstract: A method includes, in a host that stores data in a storage device, detecting an event that is indicative, statistically and not deterministically, of an imminent power shutdown in the host. A notification is sent to the storage device responsively to the detected event, so as to cause the storage device to initiate preparatory action for the imminent power shutdown.

    Abstract translation: 一种方法包括在存储设备中存储数据的主机中，检测在主机中即将发生功率关闭的统计地而不是确定地指示的事件。 响应于检测到的事件向存储设备发送通知，以使存储设备启动即将停电的准备动作。

    Memory Device Readout Using Multiple Sense Times
    5.
    发明申请
    Memory Device Readout Using Multiple Sense Times 有权
    使用多重检测时间的存储器件读数

    公开(公告)号：US20130297989A1

    公开(公告)日：2013-11-07

    申请号：US13936622

    申请日：2013-07-08

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Barak Baum ,  Naftali Sommer

    IPC: G06F11/10

    CPC classification number: G06F11/1008 ,  G11C7/06 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4091 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/26 ,  G11C16/349 ,  G11C27/005 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2211/5641

    Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.

    Abstract translation: 用于数据存储的方法包括通过将相应的存储值写入组中的存储器单元来将数据存储在一组模拟存储器单元中。 使用以第一感测时间感测存储器单元的第一读出操作读取组中的一个或多个存储器单元。 使用第二读出操作来读取组中的至少一个存储器单元，该第二读出操作以比第一感测时间长的第二感测时间感测存储器单元。 基于第一和第二读出操作的读出结果重建存储在存储单元组中的数据。

    Data storage in a memory block following WL-WL short
    10.
    发明授权
    Data storage in a memory block following WL-WL short 有权
    数据存储在WL-WL之后的存储器块中

    公开(公告)号：US09390809B1

    公开(公告)日：2016-07-12

    申请号：US14617961

    申请日：2015-02-10

    Applicant: APPLE INC.

    Inventor： Yael Shur ,  Avraham Poza Meir ,  Barak Baum ,  Eyal Gurgi

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/00

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/70 ,  G11C2029/1202

    Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

    Abstract translation: 一种方法包括定义用于应用于存储块的字线（WL）和位线（BL）的正常电压配置以及不同于正常电压配置的异常电压配置，以应用于WL和BL 当在存储器块中的至少两个WL之间找到字线到字线（WL-WL）短路时，存储块。 如果在存储块中没有发现WL-WL短路，则通过施加正常电压配置在存储块中执行数据存储操作。 如果在存储器块中发现WL-WL短路，则通过应用异常电压配置在存储块中执行数据存储操作。

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