知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.018 seconds)

    Inter-word-line programming in arrays of analog memory cells
    1.
    发明授权
    Inter-word-line programming in arrays of analog memory cells 有权
    模拟存储器单元阵列中的字间行编程

    公开(公告)号：US09105311B2

    公开(公告)日：2015-08-11

    申请号：US14332650

    申请日：2014-07-16

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

    IPC: G11C7/22 ,  G11C7/00 ,  G11C13/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/00

    CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

    Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

    Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 将所选字线中的存储单元编程的字线电压施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。

    Estimation of memory cell wear level based on saturation current
    3.
    发明授权
    Estimation of memory cell wear level based on saturation current 有权
    基于饱和电流估计存储单元磨损水平

    公开(公告)号：US08717826B1

    公开(公告)日：2014-05-06

    申请号：US13710938

    申请日：2012-12-11

    Applicant: Apple Inc.

    Inventor： Eyal Gurgi ,  Naftali Sommer ,  Yael Shur

    IPC: G11C11/34

    CPC classification number: G11C16/349

    Abstract: A method includes measuring a saturation current flowing through one or more analog memory cells. A wear level of the memory cells is deduced from the measured saturation current. Storage of data in the memory cells is configured based on the deduced wear level.

    Abstract translation: 一种方法包括测量流过一个或多个模拟存储器单元的饱和​​电流。 从测量的饱和电流推导出存储器单元的磨损水平。 基于推导的磨损水平来配置存储单元中的数据存储。

    Estimating flash quality using selective error emphasis
    4.
    发明授权
    Estimating flash quality using selective error emphasis 有权
    使用选择性错误强调估算闪光质量

    公开(公告)号：US09594615B2

    公开(公告)日：2017-03-14

    申请号：US14501081

    申请日：2014-09-30

    Applicant: APPLE INC.

    Inventor： Yael Shur ,  Eyal Gurgi ,  Moshe Neerman ,  Naftali Sommer

    IPC: G06F11/07 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C11/5692 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

    Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

    Abstract translation: 一种用于数据存储的方法包括：从存储器件读取作为相应模拟值存储在一组存储器单元中的数据，并将读出的数据中的读出错误分类为至少第一和第二不同类型，这取决于模拟 价值下降。 基于第一和第二类型的读出错误的评估数，将强调第二类型的读出错误的存储器质量分配给存储器单元组。

    Applications for inter-word-line programming
    6.
    发明授权
    Applications for inter-word-line programming 有权
    字间编程应用

    公开(公告)号：US09230680B2

    公开(公告)日：2016-01-05

    申请号：US14450903

    申请日：2014-08-04

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

    IPC: G11C16/04 ,  G11C27/00 ,  G11C7/00 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

    CPC classification number: G11C27/00 ,  G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

    Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

    Abstract translation: 一种方法包括在与各个字线相关联的行中排列的模拟存储器单元的阵列中，读取选定字线中的第一组存储器单元，包括存储至少一个状态的一个或多个存储器单元 数组中除字线以外的所选字线。 响应于读取状态设置第二组存储器单元的读出配置。 使用读出配置读取第二组存储单元。

    Inter-word-line programming in arrays of analog memory cells
    9.
    发明授权
    Inter-word-line programming in arrays of analog memory cells 有权
    模拟存储器单元阵列中的字间行编程

    公开(公告)号：US08824214B2

    公开(公告)日：2014-09-02

    申请号：US13709267

    申请日：2012-12-10

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

    IPC: G11C7/22 ,  G11C7/00

    CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

    Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

    Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 将所选字线中的存储单元编程的字线电压施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。

    FAST ANALOG MEMORY CELL READOUT USING MODIFIED BIT-LINE CHARGING CONFIGURATIONS
    10.
    发明申请
    FAST ANALOG MEMORY CELL READOUT USING MODIFIED BIT-LINE CHARGING CONFIGURATIONS 有权
    使用改进的位线充电配置的快速模拟存储器单元读数

    公开(公告)号：US20140052940A1

    公开(公告)日：2014-02-20

    申请号：US13709656

    申请日：2012-12-10

    Applicant: APPLE INC.

    Inventor： Eyal Gurgi ,  Yael Shur ,  Yoav Kasorla

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  G06F12/02

    Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

    Abstract translation: 一种用于数据存储的方法包括提供至少第一和第二读出方案，用于从连接到各个位线的一组模拟存储器单元读取存储值。 第一读出方案使用具有第一感测时间的第一位线充电配置读取存储值，并且第二读出方案使用比第一感测时间短的具有第二感测时间的第二位线充电配置来读取存储值。 针对要在一组存储器单元上执行的读取操作来评估条件。 响应于评估条件选择第一和第二读出方案中的一个。 使用所选择的读出方案从存储器单元的组中读取存储值。

Patent Agency Ranking