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    DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF
    1.
    发明申请
    DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF 审中-公开
    基于线路的双重存储器阵列和存储器单元

    公开(公告)号：US20100118602A1

    公开(公告)日：2010-05-13

    申请号：US12270056

    申请日：2008-11-13

    申请人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

    发明人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

    IPC分类号： G11C11/14

    CPC分类号： G11C5/063 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/72 ,  G11C2213/74

    摘要： A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.

    摘要翻译： 存储器阵列包括多个第一和第二源，与多个位线重叠的线，以及多个磁存储元件，每个磁存储元件分别耦合到对应的第一和第二源极线以及相应的位线。 电流可以在第一和第二方向上通过每个磁性元件被驱动，例如编程元件。 可以并入二极管以避免存储器阵列中的潜行路径。 第一二极管可以耦合在每个磁性元件和对应的第一源极线之间，第一二极管被偏置以允许读取和写入电流从相应的第一源极线流过磁性元件; 并且第二二极管可以耦合在每个磁性元件和对应的第二源极线之间，所述第二二极管被反向偏置以阻挡从对应的第二源极线读取和写入通过磁性元件的电流。

    Resistive sense memory array with partial block update capability
    2.
    发明授权
    Resistive sense memory array with partial block update capability 有权
    具有部分块更新能力的电阻式存储阵列

    公开(公告)号：US07830700B2

    公开(公告)日：2010-11-09

    申请号：US12269564

    申请日：2008-11-12

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    IPC分类号： G11C11/00

    CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

    摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY
    4.
    发明申请
    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
    具有部分块更新能力的电阻式感知存储器阵列

    公开(公告)号：US20100118587A1

    公开(公告)日：2010-05-13

    申请号：US12269564

    申请日：2008-11-12

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C11/416

    CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

    摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

    COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES
    5.
    发明申请
    COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES 有权
    具有多个接口的计算机存储器件

    公开(公告)号：US20100177562A1

    公开(公告)日：2010-07-15

    申请号：US12352713

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/14 ,  G11C7/00

    CPC分类号： G11C11/22

    摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

    摘要翻译： 各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。 在一些实施例中，主机接合第一接口。 具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。 通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY
    8.
    发明申请
    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
    具有部分块更新能力的电阻式感知存储器阵列

    公开(公告)号：US20110029714A1

    公开(公告)日：2011-02-03

    申请号：US12904653

    申请日：2010-10-14

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    IPC分类号： G06F12/00 ,  G11C11/21 ,  G11C11/16

    CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

    摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

    BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY
    9.
    发明申请
    BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY 有权
    用于电阻式感应存储器单元阵列的位设置模式

    公开(公告)号：US20100177551A1

    公开(公告)日：2010-07-15

    申请号：US12352693

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00 ,  G11C11/416

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

    摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

    Bit set modes for a resistive sense memory cell array
    10.
    发明授权
    Bit set modes for a resistive sense memory cell array 有权
    电阻读出存储单元阵列的位设置模式

    公开(公告)号：US08934281B2

    公开(公告)日：2015-01-13

    申请号：US13274876

    申请日：2011-10-17

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

    摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。