公开(公告)号：US20140177158A1

公开(公告)日：2014-06-26

申请号：US13725356

申请日：2012-12-21

Applicant: Aleksandar Aleksov ,  Shawna M. Liff

Inventor： Aleksandar Aleksov ,  Shawna M. Liff

IPC: H01L23/00 ,  G06F1/20 ,  G06F1/18

CPC classification number: H01L24/80 ,  C08G8/30 ,  C08G2261/3424 ,  C09J5/00 ,  C09J161/14 ,  C09J163/00 ,  C09J165/00 ,  C09J2203/326 ,  C09J2400/163 ,  G06F1/20 ,  G06F2200/201 ,  H01L23/02 ,  H01L23/3672 ,  H01L23/3737 ,  H01L23/433 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0384 ,  H01L2224/04026 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83484 ,  H01L2224/83487 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/171 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/05342 ,  H01L2924/095 ,  H01L2924/0665 ,  H01L2924/0715 ,  H01L2924/00012 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/07001 ,  H01L2924/014 ,  H01L2924/04953

Abstract: A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.

Abstract translation: 描述适合用作模具的热匹配复合材料。 在一个示例中，材料包括金属板和具有低于金属板的热膨胀系数（CTE）的基板，以承载微电子电路。 基板和金属板之间的粘合剂层将金属板物理地附接到基板，使得组合的金属板和基板具有比单独的基板更高的CTE。

公开(公告)号：US20180097268A1

公开(公告)日：2018-04-05

申请号：US15282050

申请日：2016-09-30

Applicant: Sasha Oster ,  Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Teles Kamgaing ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

Inventor： Sasha Oster ,  Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Teles Kamgaing ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/16 ,  H01P11/00 ,  H05K7/14

CPC classification number: H01P3/122 ,  H01P3/14 ,  H01P3/16 ,  H01P11/006

Abstract: A method of making a waveguide ribbon that includes a plurality of waveguides comprises joining a first sheet of dielectric material to a first conductive sheet of conductive material, patterning the first sheet of dielectric material to form a plurality of dielectric waveguide cores on the first conductive sheet, and coating the dielectric waveguide cores with substantially the same conductive material as the conductive sheet to form the plurality of waveguides.

公开(公告)号：US09520378B2

公开(公告)日：2016-12-13

申请号：US13725356

申请日：2012-12-21

Applicant: Aleksandar Aleksov ,  Shawna M. Liff

Inventor： Aleksandar Aleksov ,  Shawna M. Liff

IPC: H01L23/00 ,  G06F1/18 ,  G06F1/20

CPC classification number: H01L24/80 ,  C08G8/30 ,  C08G2261/3424 ,  C09J5/00 ,  C09J161/14 ,  C09J163/00 ,  C09J165/00 ,  C09J2203/326 ,  C09J2400/163 ,  G06F1/20 ,  G06F2200/201 ,  H01L23/02 ,  H01L23/3672 ,  H01L23/3737 ,  H01L23/433 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0384 ,  H01L2224/04026 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83484 ,  H01L2224/83487 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/171 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/05342 ,  H01L2924/095 ,  H01L2924/0665 ,  H01L2924/0715 ,  H01L2924/00012 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/07001 ,  H01L2924/014 ,  H01L2924/04953

Abstract: A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.

Abstract translation: 描述适合用作模具的热匹配复合材料。 在一个示例中，材料包括金属板和具有低于金属板的热膨胀系数（CTE）的基板，以承载微电子电路。 基板和金属板之间的粘合剂层将金属板物理地附接到基板，使得组合的金属板和基板具有比单独的基板更高的CTE。

公开(公告)号：US20190190106A1

公开(公告)日：2019-06-20

申请号：US16328524

申请日：2016-09-30

Applicant: TELESPHOR KAMGAING ,  SASHA OSTER ,  Georgios Dogiamis ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN ,  Brandon Rawlings

Inventor： TELESPHOR KAMGAING ,  SASHA OSTER ,  Georgios Dogiamis ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN ,  Brandon Rawlings

IPC: H01P1/04 ,  H01P1/02 ,  H01P3/12 ,  H01P11/00

CPC classification number: H01P1/042 ,  H01P1/022 ,  H01P3/12 ,  H01P3/121 ,  H01P3/122 ,  H01P11/002

Abstract: Generally, this disclosure provides apparatus and systems for coupling waveguides to a server package with a modular connector system, as well as methods for fabricating such a connector system. Such a system may be formed with connecting waveguides that turn a desired amount, which in turn may allow a server package to send a signal through a waveguide bundle in any given direction without bending waveguides.

公开(公告)号：US09875969B2

公开(公告)日：2018-01-23

申请号：US13531827

申请日：2012-06-25

Applicant: Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/12 ,  H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20170172421A1

公开(公告)日：2017-06-22

申请号：US14971800

申请日：2015-12-16

Applicant: Nadine L. Dabby ,  Adel A. Elsherbini ,  Sasha Oster ,  Braxton Lathrop ,  Aleksandar Aleksov ,  Feras Eid

Inventor： Nadine L. Dabby ,  Adel A. Elsherbini ,  Sasha Oster ,  Braxton Lathrop ,  Aleksandar Aleksov ,  Feras Eid

IPC: A61B5/0205 ,  G06F3/01 ,  A61B5/00

CPC classification number: A61B5/0205 ,  A61B5/024 ,  A61B5/08 ,  A61B5/11 ,  A61B5/113 ,  A61B5/6804 ,  A61B2562/0219 ,  A61B2562/12 ,  G06F3/011 ,  G06F3/014 ,  G06F3/017

Abstract: A sensor assembly configured to monitor one or more physiological characteristics includes a deformable substrate. The deformable substrate includes a body side interface. Substrate conductive traces are coupled with the deformable substrate. Two or more physiological sensor elements are coupled with the deformable substrate. The two or more physiological sensor elements include at least first and second sensor elements. The first sensor element includes a first piezo element in a first orientation along the deformable substrate, the first sensor element is electrically coupled with the substrate conductive traces. The second sensor element includes a second piezo element in a second orientation along the deformable substrate different than the first orientation, the second sensor element is electrically coupled with the substrate conductive traces.

公开(公告)号：US20170092412A1

公开(公告)日：2017-03-30

申请号：US14866852

申请日：2015-09-26

Applicant: Mathew J. Manusharow ,  Yonggang Li ,  William J. Lambert ,  Krishna Bharath ,  Adel A. Elsherbini ,  Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch

Inventor： Mathew J. Manusharow ,  Yonggang Li ,  William J. Lambert ,  Krishna Bharath ,  Adel A. Elsherbini ,  Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch

IPC: H01F27/28 ,  H01F41/04 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F27/24 ,  H01F41/041 ,  H01F41/042 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L21/486 ,  H01L23/49838 ,  H01L28/10 ,  H01L2224/16227

Abstract: Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.

公开(公告)号：US08621744B2

公开(公告)日：2014-01-07

申请号：US13215458

申请日：2011-08-23

Applicant: Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

Inventor： Aleksandar Aleksov ,  Gloria Alejandra Camacho-Bragado

IPC: H01F7/06

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01F17/062 ,  H01F41/16 ,  H01F2017/0073 ,  H01L23/498 ,  H01L23/50 ,  H01L23/645 ,  H01L2224/13

Abstract: A method of manufacturing an inductor for a microelectronic device comprises providing a substrate (610), forming a first plurality of inductor windings (111, 211, 411, 620, 2030) over the substrate, forming a magnetic inductor core (112, 212, 412, 810) over the first plurality of inductor windings, and forming a second plurality of inductor windings (113, 213, 413, 1010) over the magnetic inductor core. In another embodiment, the method comprises forming the inductor on a sacrificial substrate (1610) such that the inductor can subsequently be mounted onto a carrier tape (1810). In yet another embodiment, a method of manufacturing a substrate for a microelectronic device comprises forming an inductor within a build-up layer (101, 102, 103, 104) of a substrate.

Abstract translation: 制造用于微电子器件的电感器的方法包括提供衬底（610），在衬底上形成第一组多个电感器绕组（111,211,411,620,2030），形成磁感应芯（112,212， 在第一组多个电感器绕组上方形成第二多个电感器绕组（113,213,413,1010），并在磁感应器芯上形成第二多个电感器绕组（113,213,413,1010）。 在另一个实施例中，该方法包括在牺牲衬底（1610）上形成电感器，使得电感器可以随后安装在载带（1810）上。 在另一个实施例中，制造微电子器件的衬底的方法包括在衬底的堆积层（101,102,103,104）内形成电感器。

公开(公告)号：US08604353B2

公开(公告)日：2013-12-10

申请号：US13374858

申请日：2012-01-19

Applicant: Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05K1/03 ,  B23K1/20 ,  B23K31/02 ,  B05D5/12 ,  B05D3/00

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

公开(公告)号：US08227904B2

公开(公告)日：2012-07-24

申请号：US12459007

申请日：2009-06-24

Applicant: Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract translation: 多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120） ）和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140） 。 基板的任何部分都不在桥下。 该桥在第一管芯和第二管芯之间形成连接。 或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。 该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。