公开(公告)号：US20190200451A1

公开(公告)日：2019-06-27

申请号：US16328532

申请日：2016-09-29

Applicant: SASHA OSTER ,  Georgios Dogiamis ,  TELESPHOR KAMGAING ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN

Inventor： SASHA OSTER ,  Georgios Dogiamis ,  TELESPHOR KAMGAING ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  JOHANNA SWAN

IPC: H05K1/02 ,  H01L23/66 ,  H01L25/065 ,  H01L25/11 ,  H05K3/36 ,  H01L25/16 ,  H05K1/14

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L25/0655 ,  H01L25/117 ,  H01L25/16 ,  H01L25/165 ,  H05K1/141 ,  H05K3/366 ,  H05K2201/10545

Abstract: A millimeter wave (mm-wave) communication interface includes a first semiconductor package coupled to a first substrate and a second semiconductor package coupled to a second substrate. The second substrate may be coupled at approximately a 90° angle to the first substrate. The second semiconductor package may include a mm-wave die that modulates digital data on a high frequency microwave signal and a mm-wave launcher that launches the modulated high-frequency microwave signal into a waveguide member operably coupled to the second substrate. In such an implementation, the waveguide member may beneficially exit the second substrate along a longitudinal axis parallel to the principal plane of the first substrate. Advantageously, all high-frequency components are close coupled to the second substrate without the use of an intervening interface.

公开(公告)号：US20170094799A1

公开(公告)日：2017-03-30

申请号：US14866648

申请日：2015-09-25

Applicant: Shipeng Qiu ,  Shawna Liff ,  Kayleen L. Helms ,  Joshua D. Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

Inventor： Shipeng Qiu ,  Shawna Liff ,  Kayleen L. Helms ,  Joshua D. Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/00 ,  H05K3/22 ,  H05K3/30 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/189 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/036 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/22 ,  H05K3/303 ,  H05K3/326 ,  H05K3/361 ,  H05K2201/0133 ,  H05K2201/0308 ,  H05K2201/041 ,  H05K2201/047 ,  H05K2201/057 ,  H05K2201/10007 ,  H05K2201/10128 ,  H05K2203/10 ,  H05K2203/104 ,  H05K2203/105 ,  H05K2203/1105 ,  H05K2203/1194

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

公开(公告)号：US20140000377A1

公开(公告)日：2014-01-02

申请号：US13536210

申请日：2012-06-28

Applicant: Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

Inventor： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: H01L29/84 ,  G01L9/00

CPC classification number: G01L9/0042 ,  B81B7/0058 ,  B81B7/0077 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00246 ,  G01L9/0047 ,  G01L9/007 ,  G01L9/0073 ,  H01L24/19 ,  H01L29/84 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/1461 ,  H01L2924/18162

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity. Also described are various approaches to fabricating a semiconductor package having a hermetically sealed region.

Abstract translation: 描述了具有空气压力传感器的半导体封装和形成具有气压传感器的半导体封装的方法。 例如，半导体封装包括多个堆积层。 空腔设置在一个或多个堆积层中。 空气压力传感器设置在多个积聚层中，并且包括空腔和设置在空腔上方的电极。 还描述了制造具有气密密封区域的半导体封装的各种方法。

公开(公告)号：US07049704B2

公开(公告)日：2006-05-23

申请号：US10840017

申请日：2004-05-06

Applicant: Kishore K. Chakravorty ,  Johanna Swan ,  Brandon C. Barnett ,  Joseph F. Ahadian ,  Thomas P. Thomas ,  Ian Young

Inventor： Kishore K. Chakravorty ,  Johanna Swan ,  Brandon C. Barnett ,  Joseph F. Ahadian ,  Thomas P. Thomas ,  Ian Young

IPC: H01L29/40

CPC classification number: G02B6/42 ,  G02B6/4206 ,  G02B6/4212 ,  G02B6/4214 ,  G02B6/4231 ,  G02B6/43 ,  H05K1/0274 ,  H05K3/3436 ,  H05K2201/10121 ,  H05K2201/10734

Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.

Abstract translation: 允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。 使用焊料凸块技术将光学有源器件直接贴合到集成电路上。 光学器件具有直接连接到其上的透镜，以便于光耦合到光波导。 集成电路倒装芯片结合到球栅阵列（BGA）封装。 使用焊锡回流技术将BGA封装结合到PCB。

公开(公告)号：US20050121764A1

公开(公告)日：2005-06-09

申请号：US10728324

申请日：2003-12-04

Applicant: Debendra Mallik ,  Kinya Ichikawa ,  Terry Sterrett ,  Johanna Swan

Inventor： Debendra Mallik ,  Kinya Ichikawa ,  Terry Sterrett ,  Johanna Swan

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

Abstract translation: 系统可以包括集成电路管芯，耦合到集成电路管芯的集成电路封装，与集成电路管芯接触的模具化合物和集成电路封装以及耦合到集成电路封装的互连。 互连的第一部分可以与模具化合物接触，互连的第二部分可能不接触模具化合物，并且互连的第三部分可以与集成电路封装接触。

公开(公告)号：US20050121778A1

公开(公告)日：2005-06-09

申请号：US11033325

申请日：2005-01-11

Applicant: Cheng-Yi Liu ,  Johanna Swan ,  Steven Towle ,  Anna George ,  Chuan Hu

Inventor： Cheng-Yi Liu ,  Johanna Swan ,  Steven Towle ,  Anna George ,  Chuan Hu

IPC: H01L23/14 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/4871 ,  H01L23/142 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract translation: 一种方法和装置提供具有改进的散热和更容易制造的集成电路封装。 集成电路封装包括使用导热材料附着到散热器的薄化半导体管芯。 减薄的模头降低了模具/散热器组合的热阻，以改善从模具的热提取以及消除制造中的加工步骤。 此外，薄型模具变得更加柔顺，因为它承受散热器的热/机械性能，以减少模具的应力引起的开裂。

公开(公告)号：US20050090042A1

公开(公告)日：2005-04-28

申请号：US10996163

申请日：2004-11-23

Applicant: Johanna Swan ,  Bala Natarajan ,  Chien Chiang ,  Greg Atwood ,  Valluri Rao

Inventor： Johanna Swan ,  Bala Natarajan ,  Chien Chiang ,  Greg Atwood ,  Valluri Rao

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.

公开(公告)号：US06841413B2

公开(公告)日：2005-01-11

申请号：US10036389

申请日：2002-01-07

Applicant: Cheng-Yi Liu ,  Johanna Swan ,  Anna George

Inventor： Steven Towle

IPC: H01L23/14 ,  H01L23/367 ,  H01L21/44

CPC classification number: H01L24/97 ,  H01L21/4871 ,  H01L23/142 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

公开(公告)号：US20150163921A1

公开(公告)日：2015-06-11

申请号：US14102676

申请日：2013-12-11

Applicant: Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, JR. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Teles Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, JR. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Teles Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  G06F1/16 ,  H05K13/04

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

Abstract translation: 本公开一般涉及用于制造柔性微电子组件的装置，系统和方法。 在一个实例中，聚合物模制在微电子部件上，聚合物模具在模制之后呈现基本刚性的状态。 相对于微电子部件和聚合物模具形成布线层，布线层包括电耦合到微电子部件的迹线。 输入被施加到聚合物模具，聚合物模具在施加输入时从基本刚性状态转变到基本上柔性的状态。

公开(公告)号：US08230589B2

公开(公告)日：2012-07-31

申请号：US12054777

申请日：2008-03-25

Applicant: Daoqiang Lu ,  Johanna Swan ,  Henning Braunisch

Inventor： Daoqiang Lu ,  Johanna Swan ,  Henning Braunisch

IPC: H05K3/34

CPC classification number: H01S5/0261 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for aligning at least two photonic components over an interposer, and an optical package that may align such components. The method may include providing an interposer; fabricating electrical conductors passing from one surface of the interposer to an opposite surface of the interposer at selected contact positions; soldering the photonic components over the selected contact positions on the first surface, while allowing solder self-alignment. Other embodiments are described and claimed.

Abstract translation: 一种用于使插入器上的至少两个光子分量对准的方法，以及可以对准这些部件的光学封装。 该方法可以包括提供插入器; 制造从所述插入件的一个表面到选定的接触位置处的所述插入件的相对表面的电导体; 将光子组件焊接在第一表面上所选择的接触位置上，同时允许焊料自对准。 描述和要求保护其他实施例。