公开(公告)号：US08133761B2

公开(公告)日：2012-03-13

申请号：US12486596

申请日：2009-06-17

申请人： Mark A Gerber ,  Kurt P Wachtler ,  Abram M. Castro

发明人： Mark A Gerber ,  Kurt P Wachtler ,  Abram M. Castro

IPC分类号： H01L21/44

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19011

摘要： A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

摘要翻译： 具有一定尺寸（210）的一个或多个半导体插入件（201）的半导体系统（200），从第一表面延伸到第二表面的导电通孔（212），端子和附接的非回流金属螺柱（215）在 通孔的末端。 半导体插入器表面可以包括分立的电子部件或集成电路。 一个或多个半导体芯片（202,203）具有比插入件尺寸窄的尺寸（220,230）以及具有端子和非回流金属柱（224,234）的活性表面。 一个芯片被翻转连接到第一插入器表面，另一个芯片被翻转连接到第二插入器表面，使得插入器尺寸突出在芯片尺寸上。 绝缘基板（204）具有端子和回流体（242），以连接到突出插入件的螺柱。

公开(公告)号：US06107683A

公开(公告)日：2000-08-22

申请号：US075286

申请日：1998-05-08

申请人： Abram M. Castro ,  Aaron R. Castro

发明人： Abram M. Castro ,  Aaron R. Castro

IPC分类号： H01L23/28 ,  H01L23/12 ,  H01L23/24 ,  H01L23/498

CPC分类号： H01L23/24 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025

摘要： An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.

摘要翻译： 一种增强的球栅阵列衬底封装及其制造方法，其中衬底封装包括具有第一表面和与第一表面相对的第二表面的金属芯。 金属芯还包括至少一个空腔，其中定位至少一个集成电路。 电介质层固定在金属芯的第一表面上，并包括形成在其中的至少一个模腔。 此后，将导电种子层化学沉积到介电层和金属芯的第一表面的暴露部分。 在导电种子层附近，电路在第一电路图案内被电解和选择性地形成。

公开(公告)号：US5650593A

公开(公告)日：1997-07-22

申请号：US383966

申请日：1995-02-06

申请人： John R. McMillan ,  William H. Maslakow ,  Abram M. Castro

发明人： John R. McMillan ,  William H. Maslakow ,  Abram M. Castro

IPC分类号： H01L23/04 ,  H01L23/057 ,  H01L23/08 ,  H01L23/24 ,  H01L23/36 ,  H01L23/498 ,  H01L23/02 ,  H01L23/28 ,  H05K1/18 ,  H05K7/20

CPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/057 ,  H01L23/08 ,  H01L23/24 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A thermally enhanced chip carrier package with a built-in heat sink for semi-conductor integrated circuit chips. A circuit substrate is formed of a suitable thermoplastic such as PPS or LCP with a center opening and a metal attachment ring for attaching a heat sink to either the top or bottom thereof with solder. A casing is further formed on the substrate outwardly of the aperture and the heat sink mounted thereacross, the casing being comprised of the suitable thermoplastic and being chemically fused to a portion of the circuit substrate to create a moisture seal therebetween. An encapsulant for filling the cavity within the casing and a lid may also be utilized to further secure and seal the chip mounted to the heat sink secured therein.

摘要翻译： 一种热增强芯片载体封装，内置散热片，用于半导体集成电路芯片。 电路基板由诸如具有中心开口的PPS或LCP的合适的热塑性材料形成，并且金属附接环用于利用焊料将散热器附接到其顶部或底部。 壳体还进一步形成在孔的外侧，并且安装在其上的散热器，壳体由合适的热塑性材料构成，并与电路基板的一部分化学熔合以在其间产生湿气密封。 用于填充壳体内的空腔的密封剂和盖也可以用于进一步固定和密封安装到固定在其中的散热片的芯片。

公开(公告)号：US07390700B2

公开(公告)日：2008-06-24

申请号：US11400099

申请日：2006-04-07

申请人： Mark A. Gerber ,  Kurt P. Wachtler ,  Abram M. Castro

发明人： Mark A. Gerber ,  Kurt P. Wachtler ,  Abram M. Castro

IPC分类号： H01L21/44

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19011

摘要： A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

摘要翻译： 具有一定尺寸（210）的一个或多个半导体插入件（201）的半导体系统（200），从第一表面延伸到第二表面的导电通孔（212），端子和附接的非回流金属螺柱（215）在 通孔的末端。 半导体插入器表面可以包括分立的电子部件或集成电路。 一个或多个半导体芯片（202,203）具有比插入件尺寸窄的尺寸（220,230）以及具有端子和非回流金属柱（224,234）的活性表面。 一个芯片被翻转连接到第一插入器表面，另一个芯片被翻转连接到第二插入器表面，使得插入器尺寸突出在芯片尺寸上。 绝缘基板（204）具有端子和回流体（242），以连接到突出插入件的螺柱。

公开(公告)号：US06534861B1

公开(公告)日：2003-03-18

申请号：US09440630

申请日：1999-11-15

申请人： Abram M. Castro

发明人： Abram M. Castro

IPC分类号： H01L2348

CPC分类号： H01L23/3128 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.

摘要翻译： 适用于根据本发明的球栅阵列的封装衬底包括具有顶表面和底表面的导电和导热散热器，所述散热器具有穿过其形成的开口，所述槽通过所述顶表面和底表面开口。 电介质层形成在靠近狭槽的散热器的底表面上，优选地直接在其上，而没有中间的粘合剂层。 在电介质层上以电路图形选择性地形成电路。 在电介质层和电路上设置一个电阻焊接掩模，该焊接掩模具有通过其的开口露出电路的焊盘。 根据本发明的这种基板允许集成电路管芯以片上封装的方式安装在槽上，但提供可以安装焊球以便形成球栅阵列的接合焊盘。

公开(公告)号：US06248612B1

公开(公告)日：2001-06-19

申请号：US09376919

申请日：1999-08-18

申请人： Abram M. Castro ,  Aaron R. Castro

发明人： Abram M. Castro ,  Aaron R. Castro

IPC分类号： H01L2144

CPC分类号： H01L23/49816 ,  H01F41/041 ,  H01L23/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.

摘要翻译： 一种增强的球栅阵列衬底封装及其制造方法，其中衬底封装包括具有第一表面和与第一表面相对的第二表面的金属芯。 金属芯还包括至少一个空腔，其中定位至少一个集成电路。 电介质层固定在金属芯的第一表面上，并包括形成在其中的至少一个模腔。 此后，将导电种子层化学沉积到介电层和金属芯的第一表面的暴露部分。 在导电种子层附近，电路在第一电路图案内被电解并选择性地形成。

公开(公告)号：US09129955B2

公开(公告)日：2015-09-08

申请号：US12503553

申请日：2009-07-15

申请人： Abram M. Castro ,  Mark A. Gerber

发明人： Abram M. Castro ,  Mark A. Gerber

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05638 ,  H01L2224/05655 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length (111) and a first width (112), the first width being uniform along the first length, and further a pitch (114) to respective adjacent traces. The semiconductor chip has a second surface (102a) including contact pads (121); the second surface faces the first surface spaced apart by a gap (130). A conductive pillar (140) contacts each contact pad; the pillar includes a metal core (141) and a solder body (142), which connects the core to the respective trace across the gap. The pillar core (141) has an oblong cross section of a second width (151) and a second length (152) greater than the second width. Trace pitch (141) is equal to or smaller than twice the second width (151). The trace pitch is equal to or smaller than the second length (152).

摘要翻译： 组装在基板（101）上的半导体芯片（102）。 衬底具有包括具有第一长度（111）和第一宽度（112）的导电迹线（110）的第一表面（101a），第一宽度沿着第一长度是均匀的，并且还有一个间距（114）到 相应的相邻轨迹。 半导体芯片具有包括接触焊盘（121）的第二表面（102a）; 所述第二表面面向所述第一表面，间隔开间隙（130）。 导电柱（140）接触每个接触垫; 支柱包括金属芯（141）和焊料体（142），其将芯连接到穿过间隙的相应迹线。 柱芯（141）具有第二宽度（151）的长方形横截面和大于第二宽度的第二长度（152）。 痕迹间距（141）等于或小于第二宽度（151）的两倍。 迹线间距等于或小于第二长度（152）。

公开(公告)号：US06801438B1

公开(公告)日：2004-10-05

申请号：US09695353

申请日：2000-10-24

申请人： Abram M. Castro

发明人： Abram M. Castro

IPC分类号： H05K116

CPC分类号： H01L21/4846 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/056 ,  H05K1/182 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4644 ,  H05K2203/049 ,  H05K2203/107 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A process for forming a circuit pattern on a substrate includes steps of forming a number of electrical circuits on a substrate, which circuits include an electrically conductive bus that interconnects the circuits, covering the electrical circuits with a soldermask, leaving electrical contact portions exposed, electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish, and then severing the bus at locations between circuits so that the circuits are electrically isolated from each other. The process may be used to make circuit boards and especially integrated circuit packages.

摘要翻译： 用于在衬底上形成电路图案的工艺包括在衬底上形成多个电路的步骤，该电路包括导电总线，其将电路互连，用焊接掩模覆盖电路，使电接触部分露出，电镀 通过使用总线电解施加表面光洁度，然后在电路之间的位置断开总线，使得电路彼此电隔离，从而导电表面光洁度的暴露的电触点。 该过程可用于制造电路板，特别是集成电路封装。

公开(公告)号：US08530360B2

公开(公告)日：2013-09-10

申请号：US13013438

申请日：2011-01-25

申请人： Abram M. Castro

发明人： Abram M. Castro

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1379 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8184 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/01083 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.

摘要翻译： 一种装置，包括在表面（101a）上具有端子（102）的第一主体（101），每个端子具有金属连接器（110），其被成形为基本上垂直于所述表面的柱。 优选地，连接器的高度与直径的纵横比为2比1或更大，细长的中心到中心。 远离端子的连接器端（110a）被包含嵌入在第一聚合物中的金属基体的烧结膏的膜（130）覆盖。 此外，具有面向各个端子（102）的金属垫（140）的第二主体（103）。 每个连接器膜（130）与相应的垫（140）接触，由此第一主体（101）与第二主体（103）间隔开连接器柱（110）作为支座。 第二聚合物化合物（150）填充间隙的空间。

公开(公告)号：US06300165B2

公开(公告)日：2001-10-09

申请号：US09765004

申请日：2001-01-18

申请人： Abram M. Castro

发明人： Abram M. Castro

IPC分类号： H01L2144

CPC分类号： H01L23/3128 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.

摘要翻译： 适用于根据本发明的球栅阵列的封装衬底包括具有顶表面和底表面的导电和导热散热器，所述散热器具有穿过其形成的开口，所述槽通过所述顶表面和底表面开口。 电介质层形成在靠近狭槽的散热器的底表面上，优选地直接在其上，而没有中间的粘合剂层。 在电介质层上以电路图形选择性地形成电路。 在电介质层和电路上设置一个电阻焊接掩模，该焊接掩模具有通过其的开口露出电路的焊盘。 根据本发明的这种基板允许集成电路管芯以片上封装的方式安装在槽上，但是提供可以安装焊球以便形成球栅阵列的接合焊盘。