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    PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONTACTS FOR 4F2 DRAM
    1.
    发明申请
    PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONTACTS FOR 4F2 DRAM 有权

    公开(公告)号：US20250120068A1

    公开(公告)日：2025-04-10

    申请号：US18905057

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00 ,  H01L21/02 ,  H01L21/3205

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM
    2.
    发明申请
    SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM 有权

    公开(公告)号：US20250120065A1

    公开(公告)日：2025-04-10

    申请号：US18905067

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    3D NAND HIGH ASPECT RATIO STRUCTURE ETCH
    4.
    发明申请
    3D NAND HIGH ASPECT RATIO STRUCTURE ETCH 审中-公开

    公开(公告)号：US20180182777A1

    公开(公告)日：2018-06-28

    申请号：US15855465

    申请日：2017-12-27

    Applicant: Applied Materials, Inc.

    Inventor： Zhenjiang CUI ,  Hanshen ZHANG ,  Anchuan WANG ,  Zhijun CHEN ,  Nitin K. INGLE

    IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/29 ,  H01L27/11556 ,  H01L21/67

    Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about −100° C. to about 100° C.

    SELF-ALIGNED BIT LINE FOR 4F2 DRAM
    6.
    发明申请
    SELF-ALIGNED BIT LINE FOR 4F2 DRAM 有权

    公开(公告)号：US20250120069A1

    公开(公告)日：2025-04-10

    申请号：US18905062

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    DUAL WORK FUNCTION WORD LINE FOR 4F2
    7.
    发明申请
    DUAL WORK FUNCTION WORD LINE FOR 4F2 有权

    公开(公告)号：US20250107068A1

    公开(公告)日：2025-03-27

    申请号：US18886692

    申请日：2024-09-16

    Applicant: Applied Materials, Inc.

    Inventor： Tong LIU ,  Sony VARGHESE ,  Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00 ,  H01L21/762

    Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

    STORAGE NODE CONTACT (SNC) JUNCTION FORMATION FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    8.
    发明申请
    STORAGE NODE CONTACT (SNC) JUNCTION FORMATION FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权

    公开(公告)号：US20250063716A1

    公开(公告)日：2025-02-20

    申请号：US18781132

    申请日：2024-07-23

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN

    IPC: H10B12/00

    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a stacked semiconductor structure is provided, where the stacked semiconductor structure includes a plurality of unit stacks formed on a substrate. Each unit stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. A lateral recess of the capacitor portion is open to a first opening through the unit stack. The method includes conformally depositing, in the lateral recess, a doped silicon layer on a lateral end of the semiconductor layer, performing a thermal annealing process after forming the doped silicon layer on the second lateral end. The method further includes forming a capacitor where the lateral recess was disposed, the capacitor contacting the doped silicon layer on the second lateral end of the semiconductor layer.

    DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT
    9.
    发明公开
    DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT 审中-公开

    公开(公告)号：US20240341090A1

    公开(公告)日：2024-10-10

    申请号：US18608917

    申请日：2024-03-18

    Applicant: Applied Materials, Inc.

    Inventor： Sony VARGHESE ,  Tong LIU ,  Zhijun CHEN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor structure includes a first active region and a second active region on a substrate, a metal plug electrically connected to the first active region via a contact layer and an interface layer, a bit line electrically connected to the second active region via a bit line contact plug, and a bit line spacer encapsulating the bit line, wherein the first active region and the second active region are lightly n-type doped, the substrate is p-type doped, and the contact layer is epitaxially grown and n-type doped with a graded doping profile that increases from an interface with the first active region to an interface with the interface layer.

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