公开(公告)号：US20250167001A1

公开(公告)日：2025-05-22

申请号：US18912134

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Tong LIU ,  Sony VARGHESE ,  Madhur Singh SACHAN ,  Keiichi NAKAZAWA ,  Zhiyu HUANG

IPC: H01L21/308 ,  H01L21/311

Abstract: A method of forming a pattern in a device structure formed on a substrate includes forming one or more patterning layers over a surface of a device structure formed on the substrate, forming patterning features in the one or more patterning layers, depositing a non-conformal film layer over a surface of the one or more patterning layers and the patterning features, and etching a portion of a device feature of the plurality of device features that is exposed within each film layer opening formed within the patterning features. Each of the patterning features are disposed over at least a portion of a device feature of a plurality of device features, and each of the patterning features comprise a feature opening that comprises a first critical dimension (CD) that is greater than the first lateral dimension.

公开(公告)号：US20250107068A1

公开(公告)日：2025-03-27

申请号：US18886692

申请日：2024-09-16

Applicant: Applied Materials, Inc.

Inventor： Tong LIU ,  Sony VARGHESE ,  Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B12/00 ,  H01L21/762

Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

公开(公告)号：US20240341090A1

公开(公告)日：2024-10-10

申请号：US18608917

申请日：2024-03-18

Applicant: Applied Materials, Inc.

Inventor： Sony VARGHESE ,  Tong LIU ,  Zhijun CHEN ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor structure includes a first active region and a second active region on a substrate, a metal plug electrically connected to the first active region via a contact layer and an interface layer, a bit line electrically connected to the second active region via a bit line contact plug, and a bit line spacer encapsulating the bit line, wherein the first active region and the second active region are lightly n-type doped, the substrate is p-type doped, and the contact layer is epitaxially grown and n-type doped with a graded doping profile that increases from an interface with the first active region to an interface with the interface layer.

公开(公告)号：US20250166994A1

公开(公告)日：2025-05-22

申请号：US18601809

申请日：2024-03-11

Applicant: Applied Materials, Inc.

Inventor： Zhiyu HUANG ,  Tong LIU ,  Madhur Singh SACHAN ,  Sony VARGHESE ,  Keiichi NAKAZAWA

IPC: H01L21/033 ,  G03F7/00 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a pattern in a device structure formed on a substrate includes forming one or more patterning layers over a surface of a device structure formed on the substrate, forming patterning features in the one or more patterning layers, depositing a film layer over a surface of the one or more patterning layers and the patterning features, and etching at least a portion of a first device feature of a plurality of device features that is exposed within each of film layer openings formed within the patterning features.

公开(公告)号：US20250098149A1

公开(公告)日：2025-03-20

申请号：US18884775

申请日：2024-09-13

Applicant: Applied Materials, Inc.

Inventor： Tong LIU ,  Sony VARGHESE

IPC: H10B12/00 ,  H01L29/08

Abstract: The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the channels have at least one source/drain region and a channel body disposed between the first end and the second end. Arrays include where the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the at least one source/drain region.

公开(公告)号：US20250081432A1

公开(公告)日：2025-03-06

申请号：US18816103

申请日：2024-08-27

Applicant: Applied Materials, Inc.

Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Tong LIU ,  Sony VARGHESE ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B12/00 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Vertical cell dynamic random-access memory (DRAM) arrays and methods of forming arrays with improved stability and word line resistivity are provided. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels. In addition, arrays include a bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction. Arrays include a gate formed around at least a portion of the plurality of channels and the bridge.

公开(公告)号：US20240332031A1

公开(公告)日：2024-10-03

申请号：US18193455

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Feng QIAO ,  Hailong ZHOU ,  Qian FU ,  Sangjun PARK ,  Jayoung CHOI ,  Radhe AGARWAL ,  Tong LIU

IPC: H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/32137 ,  H01L21/3065 ,  H01L21/32139

Abstract: A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.

公开(公告)号：US20250098142A1

公开(公告)日：2025-03-20

申请号：US18812803

申请日：2024-08-22

Applicant: Applied Materials, Inc.

Inventor： Tong LIU ,  Sony VARGHESE

IPC: H10B12/00

Abstract: A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a cell transistor having a source region electrically connected to a bit line extending in the first direction, a drain region, a word line layer, a lower channel layer electrically connected to the source region and the drain region and disposed below the word line layer in the first direction, and an upper channel layer electrically connected to the source region and the drain region and disposed above the word line layer in the first direction, and a cell capacitor electrically connected to the drain region, and a plurality of inter-level isolation layers, each separating adjacent memory levels of the plurality of memory levels.