公开(公告)号：US20240332031A1

公开(公告)日：2024-10-03

申请号：US18193455

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Feng QIAO ,  Hailong ZHOU ,  Qian FU ,  Sangjun PARK ,  Jayoung CHOI ,  Radhe AGARWAL ,  Tong LIU

IPC: H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/32137 ,  H01L21/3065 ,  H01L21/32139

Abstract: A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.