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    TITANIUM OXIDE ETCH
    2.
    发明申请
    TITANIUM OXIDE ETCH 有权
    氧化钛蚀刻

    公开(公告)号：US20150206764A1

    公开(公告)日：2015-07-23

    申请号：US14157724

    申请日：2014-01-17

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Xikun WANG ,  Lin XU ,  Anchuan WANG ,  Nitin K. INGLE

    IPC: H01L21/311

    CPC classification number: H01L21/31122 ,  H01J37/32357 ,  H01L21/0337

    Abstract: Methods of selectively etching titanium oxide relative to silicon oxide, silicon nitride and/or other dielectrics are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and/or a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium oxide. The plasmas effluents react with exposed surfaces and selectively remove titanium oxide while very slowly removing other exposed materials. A direction sputtering pretreatment is performed prior to the remote plasma etch and enables an increased selectivity as well as a directional selectivity. In some embodiments, the titanium oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

    Abstract translation: 描述了相对于氧化硅，氮化硅和/或其它电介质来选择性地蚀刻氧化钛的方法。 所述方法包括使用由含氟前体和/或含氯前体形成的等离子体流出物的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与氧化钛反应。 等离子体流出物与暴露的表面反应并选择性地去除氧化钛，同时非常缓慢地除去其它暴露的材料。 在远程等离子体蚀刻之前执行方向溅射预处理，并且能够提高选择性以及方向选择性。 在一些实施方案中，钛氧化物蚀刻选择性部分地来自位于远程等离子体和基板处理区域之间的离子抑制元件的存在。

    GATE CONTACT OVER ACTIVE REGIONS
    3.
    发明申请
    GATE CONTACT OVER ACTIVE REGIONS 有权

    公开(公告)号：US20210249270A1

    公开(公告)日：2021-08-12

    申请号：US17242375

    申请日：2021-04-28

    Applicant: Applied Materials, Inc.

    Inventor： Gaurav THAREJA ,  Keyvan KASHEFIZADEH ,  Xikun WANG ,  Anchuan WANG ,  Sanjay NATARAJAN ,  Sean M. SEUTTER ,  Dong WU

    IPC: H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/283

    Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

    CONTACT FORMATION PROCESS FOR CMOS DEVICES
    5.
    发明公开
    CONTACT FORMATION PROCESS FOR CMOS DEVICES 审中-公开

    公开(公告)号：US20230377997A1

    公开(公告)日：2023-11-23

    申请号：US18123783

    申请日：2023-03-20

    Applicant: Applied Materials, Inc.

    Inventor： Nicolas Louis BREIL ,  Balasubramanian PRANATHARTHIHARAN ,  Benjamin COLOMBEAU ,  Anchuan WANG

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L21/823871 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76895

    Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

    PROTECTIVE SILICON OXIDE PATTERNING
    10.
    发明申请
    PROTECTIVE SILICON OXIDE PATTERNING 审中-公开
    保护硅氧化物图案

    公开(公告)号：US20150371861A1

    公开(公告)日：2015-12-24

    申请号：US14312202

    申请日：2014-06-23

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Zihui LI ,  Zhijun CHEN ,  Anchuan WANG

    IPC: H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/3086 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/31144

    Abstract: A method of patterning a substrate is described and include two possible layers which may be easily integrated into a photoresist patterning process flow and avoid an observed photoresist peeling problems. A conformal carbon layer or a conformal silicon-carbon-nitrogen layer may be formed between an underlying silicon oxide layer and an overlying photoresist layer. Either inserted layer may avoid remotely-excited fluorine etchants from diffusing through the photoresist and chemically degrading the silicon oxide. The conformal carbon layer may be removed at the same time as the photoresist and the conformal silicon-carbon-nitrogen layer may be removed at the same time as the silicon oxide, limiting process complexity.

    Abstract translation: 描述了图案化衬底的方法，并且包括两个可能的层，其可以容易地集成到光致抗蚀剂图案化工艺流程中并避免观察到的光刻胶剥离问题。 可以在下面的氧化硅层和上覆的光致抗蚀剂层之间形成保形碳层或保形硅 - 碳 - 氮层。 任一插入层可以避免远程激发的氟蚀刻剂通过光致抗蚀剂扩散并化学降解氧化硅。 可以在与硅氧化物同时去除光致抗蚀剂和共形硅 - 碳 - 氮层的同时去除共形碳层，从而限制了工艺的复杂性。

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