公开(公告)号：US20150206764A1

公开(公告)日：2015-07-23

申请号：US14157724

申请日：2014-01-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Xikun WANG ,  Lin XU ,  Anchuan WANG ,  Nitin K. INGLE

IPC: H01L21/311

CPC classification number: H01L21/31122 ,  H01J37/32357 ,  H01L21/0337

Abstract: Methods of selectively etching titanium oxide relative to silicon oxide, silicon nitride and/or other dielectrics are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and/or a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium oxide. The plasmas effluents react with exposed surfaces and selectively remove titanium oxide while very slowly removing other exposed materials. A direction sputtering pretreatment is performed prior to the remote plasma etch and enables an increased selectivity as well as a directional selectivity. In some embodiments, the titanium oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

Abstract translation: 描述了相对于氧化硅，氮化硅和/或其它电介质来选择性地蚀刻氧化钛的方法。 所述方法包括使用由含氟前体和/或含氯前体形成的等离子体流出物的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与氧化钛反应。 等离子体流出物与暴露的表面反应并选择性地去除氧化钛，同时非常缓慢地除去其它暴露的材料。 在远程等离子体蚀刻之前执行方向溅射预处理，并且能够提高选择性以及方向选择性。 在一些实施方案中，钛氧化物蚀刻选择性部分地来自位于远程等离子体和基板处理区域之间的离子抑制元件的存在。

公开(公告)号：US20210249270A1

公开(公告)日：2021-08-12

申请号：US17242375

申请日：2021-04-28

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Keyvan KASHEFIZADEH ,  Xikun WANG ,  Anchuan WANG ,  Sanjay NATARAJAN ,  Sean M. SEUTTER ,  Dong WU

IPC: H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/283

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US20200258744A1

公开(公告)日：2020-08-13

申请号：US16442797

申请日：2019-06-17

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Keyvan KASHEFIZADEH ,  Xikun WANG ,  Anchuan WANG ,  Sanjay NATARAJAN ,  Sean M. SEUTTER ,  Dong Wu

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/49 ,  H01L29/45

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.