公开(公告)号：US09929076B2

公开(公告)日：2018-03-27

申请号：US13913183

申请日：2013-06-07

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/492

CPC分类号： H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

公开(公告)号：US20160104661A9

公开(公告)日：2016-04-14

申请号：US13913183

申请日：2013-06-07

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

摘要翻译： 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US09214419B2

公开(公告)日：2015-12-15

申请号：US14194502

申请日：2014-02-28

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC分类号： H01L21/44 ,  H01L23/495 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

摘要： A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

摘要翻译： 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US08987878B2

公开(公告)日：2015-03-24

申请号：US12916086

申请日：2010-10-29

申请人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/495 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

摘要翻译： 无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。 衬底和外延层的总厚度可以小于25微米。 焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

公开(公告)号：US08796858B2

公开(公告)日：2014-08-05

申请号：US13488424

申请日：2012-06-04

申请人： Tao Feng ,  Yueh-Se Ho

发明人： Tao Feng ,  Yueh-Se Ho

IPC分类号： H01L23/48

CPC分类号： H01L21/561 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.

摘要翻译： 公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。 载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘 。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。 厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

公开(公告)号：US08586414B2

公开(公告)日：2013-11-19

申请号：US12968159

申请日：2010-12-14

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

IPC分类号： H01L21/00

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

摘要翻译： 半导体封装及其制造方法包括具有管芯焊盘的引线框架和设置在顶表面上的大致V形槽的源极引线。 设置在芯片焊盘上的半导体芯片。 连接到芯片的顶表面电极的金属板具有在V沟槽中终止的弯曲延伸部，与V沟槽侧壁中的至少一个接触。

公开(公告)号：US08513784B2

公开(公告)日：2013-08-20

申请号：US12726892

申请日：2010-03-18

申请人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

发明人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。

公开(公告)号：US20130210195A1

公开(公告)日：2013-08-15

申请号：US13547358

申请日：2012-07-12

申请人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

IPC分类号： H01L21/78

CPC分类号： H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

摘要： A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

摘要翻译： WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

公开(公告)号：US20130130443A1

公开(公告)日：2013-05-23

申请号：US13302219

申请日：2011-11-22

申请人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

发明人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/04034 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05794 ,  H01L2224/058 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06164 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/053 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

摘要翻译： 本发明一般涉及超薄芯片的封装方法，更具体地说，本发明涉及一种用于在晶片级封装工艺中封装具有焊球热压缩的超薄芯片的方法。 该方法开始于将焊球设置在形成在半导体晶片的前表面的半导体芯片的前表面上的金属焊盘上。 通过加热晶片来软化焊球，压力板在焊球的顶端施加压力，从而在焊球的顶端形成共面顶表面。 模具化合物沉积在晶片的前表面上，其中焊球的顶端被暴露。 然后将晶片从其背面研磨以减小其厚度以实现超薄芯片。

公开(公告)号：US20120205803A1

公开(公告)日：2012-08-16

申请号：US13454342

申请日：2012-04-24

申请人： Ming Sun ,  Yueh Se Ho

发明人： Ming Sun ,  Yueh Se Ho

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L23/3677 ,  H01L23/49844 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

摘要： This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

摘要翻译： 本发明公开了一种用于容纳垂直半导体芯片的电子封装件，该电子封装件包括具有通孔连接器的层压板和分布在连接到通孔连接器的叠层板的多层上的导电迹线。 所述半导体芯片具有至少一个连接到所述导电迹线的电极，所述至少一个电极与所述层压板上的不同层上的所述导电迹线电连接，并且所述通孔连接器消散由所述垂直半导体产生的热量。 连接到通孔连接器的球栅阵列（BGA），所述通孔连接器用作在封装的底表面处的接触件，用于安装在布置在印刷电路板（PCB）上的电端子上，其中所述层压板的热膨胀系数在基本相同的范围内 该PCB由此使BGA与电气端子具有可靠的电接触。