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    Metal Gate Structure
    2.
    发明申请
    Metal Gate Structure 有权
    金属门结构

    公开(公告)号：US20130049109A1

    公开(公告)日：2013-02-28

    申请号：US13214996

    申请日：2011-08-22

    Applicant: Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

    Inventor： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

    IPC: H01L27/088 ,  H01L21/283 ,  H01L23/48

    CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/31105 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.

    Abstract translation: 金属栅极结构包括部分地填充金属栅极结构的沟槽的金属层。 金属层包括第一金属侧壁，第二金属侧壁和金属底层。 通过在回蚀处理中采用不均匀的保护层，第一金属侧壁的厚度小于金属底层的厚度，第二金属侧壁的厚度小于金属底层的厚度。 薄的侧壁为后续的金属填充过程提供了额外的空间。

    Gate Structures
    3.
    发明申请
    Gate Structures 有权
    门结构

    公开(公告)号：US20120319192A1

    公开(公告)日：2012-12-20

    申请号：US13599507

    申请日：2012-08-30

    Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

    Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

    IPC: H01L27/092 ,  H01L27/088

    CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

    Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

    Abstract translation: 一种装置包括第一装置。 第一装置包括第一突起和第一栅极结构，第一突起从衬底向上延伸并且在其中具有第一沟道区域，并且第一栅极结构接合与第一沟道区相邻的第一突起。 第一结构包括在第一通道区域上的开口，以及设置在开口中的具有低电阻率的保形的纯金属。 该装置还包括第二装置，其包括第二突起和第二栅极结构，第二突起从基板向上延伸并且在其中具有第二通道区域，并且第二栅极结构接合与第二通道区域相邻的第二突出部。 第二结构包括设置在第二通道区域上的硅化物，其中硅化物包括设置在开口中的相同金属的金属。

    METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN
    4.
    发明申请
    METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN 有权
    用于金属栅格形成的方法和系统，具有宽的金属栅格膜

    公开(公告)号：US20120217578A1

    公开(公告)日：2012-08-30

    申请号：US13466665

    申请日：2012-05-08

    Applicant: Peng-Soon Lim ,  Meng-Hsuan Chan ,  Kuang-Yuan Hsu

    Inventor： Peng-Soon Lim ,  Meng-Hsuan Chan ,  Kuang-Yuan Hsu

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621

    Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

    Abstract translation: 一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。 金属层包括比底部更薄的底部部分和侧壁部分。 所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。 不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比 底部。

    METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS
    7.
    发明申请
    METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS 有权
    在门过程中形成金属门的方法

    公开(公告)号：US20100081262A1

    公开(公告)日：2010-04-01

    申请号：US12411546

    申请日：2009-03-26

    Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

    Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Chien-Hao Chen ,  Chi-Chun Chen

    IPC: H01L21/3205 ,  H01L21/20 ,  H01L21/31

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66636

    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

    Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供具有第一区域和第二区域的衬底，分别在第一和第二区域中形成第一和第二栅极堆叠，第一栅极堆叠包括第一虚拟栅极和 所述第二栅极堆叠包括第二伪栅极，去除所述第一栅极堆叠中的所述第一伪栅极，从而形成第一沟槽并且去除所述第二栅极堆叠中的所述第二伪栅极，从而形成第二沟槽，从而形成第一栅极堆叠中的第一金属层 沟槽，并且在第二沟槽中，去除第一沟槽中的第一金属层的至少一部分，在第一沟槽的其余部分和第二沟槽的其余部分中形成第二金属层，回流第二金属层，以及 进行化学机械抛光（CMP）。

    Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures
    8.
    发明申请
    Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
    形成具有n-MOSFET和p-MOSFET晶体管的集成电路器件的方法，其具有升高和硅化源极/漏极结构

    公开(公告)号：US20080096336A1

    公开(公告)日：2008-04-24

    申请号：US11583500

    申请日：2006-10-18

    Applicant: Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    Inventor： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    IPC: H01L21/337

    CPC classification number: H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

    Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

    Abstract translation: n-FET和p-FET各自具有升高的源极/漏极结构。 可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。 可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。 即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。 对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。 此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化 ， 分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。 在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

    Metal gate structure of a field effect transistor
    10.
    发明授权
    Metal gate structure of a field effect transistor 有权
    场效应晶体管的金属栅极结构

    公开(公告)号：US08779530B2

    公开(公告)日：2014-07-15

    申请号：US12643414

    申请日：2009-12-21

    Applicant: Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

    Inventor： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

    IPC: H01L29/78

    CPC classification number: H01L29/4966 ,  H01L21/28008 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance.

    Abstract translation: 本发明涉及集成电路制造，更具体地涉及具有低电阻金属栅电极的场效应晶体管。 用于场效应晶体管的栅电极的示例性结构包括由具有凹部和第一电阻的第一金属材料形成的下部; 以及由具有突起和第二电阻的第二金属材料形成的上部，其中所述突起延伸到所述凹部中，其中所述第二电阻低于所述第一电阻。

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