公开(公告)号：US10331602B2

公开(公告)日：2019-06-25

申请号：US15448910

申请日：2017-03-03

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Seiji Goto

IPC分类号： G06F3/00 ,  G06F13/40 ,  H04L12/00 ,  G06F13/36 ,  G06F17/50

摘要： A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.

公开(公告)号：US10325986B2

公开(公告)日：2019-06-18

申请号：US15298913

申请日：2016-10-20

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC分类号： H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

公开(公告)号：US10236286B2

公开(公告)日：2019-03-19

申请号：US15595306

申请日：2017-05-15

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Katsuyoshi Matsuura ,  Junichi Ariyoshi

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/07 ,  H01L27/06 ,  H01L27/11517 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.

公开(公告)号：US10014363B2

公开(公告)日：2018-07-03

申请号：US15402367

申请日：2017-01-10

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Taiji Ema ,  Nobuhiro Misawa ,  Kazuyuki Kumeno ,  Makoto Yasuda

IPC分类号： H01L27/06 ,  H01L29/8605 ,  H01L49/02 ,  H01L27/08

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

公开(公告)号：US09966130B2

公开(公告)日：2018-05-08

申请号：US15634857

申请日：2017-06-27

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Robert Rogenmoser ,  Damodar R. Thummalapally

IPC分类号： G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L29/78 ,  H01L29/10

CPC分类号： G11C11/418 ,  G11C5/063 ,  G11C5/14 ,  G11C7/02 ,  G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/7833 ,  H01L29/7838

摘要： An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.

公开(公告)号：US09793172B2

公开(公告)日：2017-10-17

申请号：US15298933

申请日：2016-10-20

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/425 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L21/04 ,  H01L21/82 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

公开(公告)号：US20170293583A1

公开(公告)日：2017-10-12

申请号：US15448910

申请日：2017-03-03

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Seiji Goto

IPC分类号： G06F13/40 ,  G06F17/50 ,  G06F13/36

CPC分类号： G06F13/4022 ,  G06F13/36 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/84

摘要： A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.

公开(公告)号：US09773733B2

公开(公告)日：2017-09-26

申请号：US15066309

申请日：2016-03-10

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Taiji Ema ,  Makoto Yasuda ,  Kazuhiro Mizutani

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L31/113 ,  H01L27/01 ,  H01L23/528 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/792

CPC分类号： H01L23/528 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/11573 ,  H01L29/42348 ,  H01L29/792

摘要： There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

公开(公告)号：US20170186704A1

公开(公告)日：2017-06-29

申请号：US15459199

申请日：2017-03-15

申请人： MIE FUJITSU SEMICONDUCTOR LIMITED

发明人： Jun Sakuma ,  Hideaki Matsumura ,  Tadashi Ohshima

IPC分类号： H01L23/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/01007 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

公开(公告)号：US09368624B2

公开(公告)日：2016-06-14

申请号：US14808122

申请日：2015-07-24

申请人： MIE Fujitsu Semiconductor Limited

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。