公开(公告)号：US10217838B2

公开(公告)日：2019-02-26

申请号：US15963598

申请日：2018-04-26

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/283

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

公开(公告)号：US09991300B2

公开(公告)日：2018-06-05

申请号：US15658907

申请日：2017-07-25

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Teymur Bakhishev ,  Lingquan Wang ,  Dalong Zhao ,  Pushkar Ranade ,  Scott E. Thompson

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/146 ,  H04N5/3745 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/14616 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7833 ,  H01L29/7838 ,  H04N5/3745

Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

公开(公告)号：US09508728B2

公开(公告)日：2016-11-29

申请号：US15003151

申请日：2016-01-21

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Thomas Hoffmann ,  Pushkar Ranade ,  Scott E. Thompson

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L27/1108 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966

Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

公开(公告)号：US09496261B2

公开(公告)日：2016-11-15

申请号：US13969938

申请日：2013-08-19

Applicant: MIE Fujitsu Semiconductor Limited

Inventor： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson ,  Sachrin R. Sonkusale ,  Weimin Zhang

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/7833

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract translation: 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的σVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。

公开(公告)号：US09478571B1

公开(公告)日：2016-10-25

申请号：US14286063

申请日：2014-05-23

Applicant: MIE Fujitsu Semiconductor Limited

Inventor： Teymur Bakhishev ,  Lingquan Wang ,  Dalong Zhao ,  Pushkar Ranade ,  Scott E. Thompson

IPC: H01L21/336 ,  H01L27/146 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/14616 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7833 ,  H01L29/7838 ,  H04N5/3745

Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Abstract translation: 提供半导体器件和制造这种器件的方法。 这些器件包括由沟道长度和栅极结构分开的一种导电类型的源极和漏极区域。 器件还包括形成在源极和漏极区域之间的器件区域中的一种导电类型的沟道区域和形成在沟道区域下方以及源极和漏极区域之间的另一导电类型的屏蔽区域。 在操作中，沟道区域响应于栅极结构处的偏置电压而形成栅极结构下方的表面耗尽区域，在沟道区域和屏蔽区域的界面处的掩埋耗尽区域，以及在沟道区域之间的掩埋沟道区域 表面耗尽区域和掩埋耗尽区域，其中掩埋耗尽区域基本上位于沟道区域中。

公开(公告)号：US09418987B2

公开(公告)日：2016-08-16

申请号：US14296527

申请日：2014-06-05

Applicant: MIE Fujitsu Semiconductor Limited

Inventor： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

IPC: H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7836

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.

Abstract translation: 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的σVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。 可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 结果是独立控制VT（具有较低的σVT）和VDD的能力，从而使给定器件的体偏压可以与VT分开调谐。

公开(公告)号：US20160211346A1

公开(公告)日：2016-07-21

申请号：US15082926

申请日：2016-03-28

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083

Abstract: Semiconductor structures can be fabricated by implanting a screen layer into a substrate, with the screen layer formed at least in part from a low diffusion dopant species. An epitaxial channel of silicon or silicon germanium is formed above the screen layer, and the same or different dopant species is diffused from the screen layer into the epitaxial channel layer to form a slightly depleted channel (SDC) transistor. Such transistors have inferior threshold voltage matching characteristics compared to deeply depleted channel (DDC) transistors, but can be more easily matched to legacy doped channel transistors in system on a chip (SoC) or multiple transistor semiconductor die.

Abstract translation: 半导体结构可以通过将屏幕层注入到衬底中来制造，其中屏幕层至少部分地由低扩散掺杂物种形成。 在屏幕层上方形成硅或硅锗的外延沟道，并且相同或不同的掺杂物质从屏幕层扩散到外延沟道层中以形成稍微耗尽的沟道（SDC）晶体管。 与深度耗尽的通道（DDC）晶体管相比，这种晶体管具有较差的阈值电压匹配特性，但是可以更容易地与芯片（SoC）或多晶体管半导体管芯中的系统中的传统掺杂沟道晶体管匹配。

公开(公告)号：US20160181370A1

公开(公告)日：2016-06-23

申请号：US14977887

申请日：2015-12-22

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L27/092

CPC classification number: H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract translation: 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，良好掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：US09299698B2

公开(公告)日：2016-03-29

申请号：US13926555

申请日：2013-06-25

Applicant: MIE Fujitsu Semiconductor Limited

Inventor： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract translation: 半导体结构包括第一，第二和第三晶体管元件，每个具有同时形成在其中的第一屏蔽区域。 第二屏蔽区域形成在第二和第三晶体管元件中，使得在第二晶体管元件中存在与第三晶体管元件中的第二屏蔽区域不同的屏蔽区域的至少一个特性。 不同的特征包括掺杂浓度和植入深度。 此外，可以通过在第二和第三晶体管元件中同时植入第二屏蔽区域，然后将另外的掺杂剂注入第三晶体管元件的第二屏蔽区域来实现不同的特性。

公开(公告)号：US09224733B2

公开(公告)日：2015-12-29

申请号：US14046234

申请日：2013-10-04

Applicant: MIE Fujitsu Semiconductor Limited

Inventor： Lucian Shifren ,  Pushkar Ranade ,  Sachin R. Sonkusale

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/0922

Abstract: A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.

Abstract translation: 半导体结构包括具有栅极区域的第一PMOS晶体管元件，栅极区域与PMOS功能相关联的第一栅极金属和具有与NMOS功能相关联的第二金属的栅极区域的第一NMOS晶体管元件。 第一PMOS晶体管元件和第一NMOS晶体管元件形成第一CMOS器件。 该半导体结构还包括第二PMOS晶体管，该第二PMOS晶体管部分地通过与NMOS功能相关联的第二金属的第一NMOS晶体管元件并行形成，以形成具有与第一CMOS器件不同的工作特性的第二CMOS器件。