公开(公告)号：US10325986B2

公开(公告)日：2019-06-18

申请号：US15298913

申请日：2016-10-20

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC分类号： H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

公开(公告)号：US09793172B2

公开(公告)日：2017-10-17

申请号：US15298933

申请日：2016-10-20

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/425 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L21/04 ,  H01L21/82 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

公开(公告)号：US09368624B2

公开(公告)日：2016-06-14

申请号：US14808122

申请日：2015-07-24

申请人： MIE Fujitsu Semiconductor Limited

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US20160163823A1

公开(公告)日：2016-06-09

申请号：US15047052

申请日：2016-02-18

申请人： Mie Fujitsu Semiconductor Limited

发明人： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U.C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC分类号： H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

摘要： A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element

摘要翻译： 半导体结构包括第一，第二和第三晶体管元件，每个具有同时形成在其中的第一屏蔽区域。 第二屏蔽区域形成在第二和第三晶体管元件中，使得在第二晶体管元件中存在与第三晶体管元件中的第二屏蔽区域不同的屏蔽区域的至少一个特性。 不同的特征包括掺杂浓度和植入深度。 另外，可以通过在第二和第三晶体管元件中同时植入第二屏蔽区域，然后将另外的掺杂剂注入第三晶体管元件的第二屏蔽区域来实现不同的特性

公开(公告)号：US20160141292A1

公开(公告)日：2016-05-19

申请号：US15003151

申请日：2016-01-21

申请人： Mie Fujitsu Semiconductor Limited

发明人： Thomas Hoffmann ,  Pushkar Ranade ,  Scott E. Thompson

IPC分类号： H01L27/11 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L27/1108 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966

摘要： A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

摘要翻译： 半导体器件包括具有在其中形成有第一有源区和第二有源区的半导体表面的衬底，其中第一有源区由表面处的基本上未掺杂的层和在第一有源区下面的第一导电类型的高掺杂屏蔽层 第一基本上未掺杂的层，并且第二有源区由表面处的第二基本上未掺杂的层和在第二基本未掺杂的层下面的第二导电类型的第二高掺杂屏蔽层组成。 该半导体器件还包括形成在每个第一有源区中的栅极堆叠，而第二有源区由至少一个栅极电介质层和金属层组成，其中金属具有相对于 半导体表面。

公开(公告)号：US09281248B1

公开(公告)日：2016-03-08

申请号：US14266115

申请日：2014-04-30

申请人： MIE Fujitsu Semiconductor Limited

发明人： Thomas Hoffmann ,  Pushkar Ranade ,  Scott E. Thompson

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1108 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966

摘要： A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

摘要翻译： 半导体器件包括具有在其中形成有第一有源区和第二有源区的半导体表面的衬底，其中第一有源区由表面处的基本上未掺杂的层和在第一有源区下面的第一导电类型的高掺杂屏蔽层 第一基本上未掺杂的层，并且第二有源区由表面处的第二基本上未掺杂的层和在第二基本未掺杂的层下面的第二导电类型的第二高掺杂屏蔽层组成。 该半导体器件还包括形成在每个第一有源区中的栅极堆叠，而第二有源区由至少一个栅极电介质层和金属层组成，其中金属具有相对于 半导体表面。

公开(公告)号：US20150340460A1

公开(公告)日：2015-11-26

申请号：US14811985

申请日：2015-07-29

申请人： MIE Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Lance Scudder

IPC分类号： H01L29/66 ,  H01L21/265

CPC分类号： H01L21/823412 ,  H01L21/265 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7836

摘要： An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1 The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5×1017 dopant atoms per cm3.

摘要翻译： 具有阈值电压设置掺杂剂结构的高级晶体管包括具有长度Lg的阱，并且阱掺杂以具有掺杂剂的第一浓度。 筛选区域位于阱和栅极之间，并且具有大于每立方厘米5×1018掺杂剂原子的第二浓度的掺杂剂。 通过放置位于筛选区域上方的阈值电压偏移平面来形成阈值电压设定区域。 阈值电压设定区域可以通过增量掺杂形成，并具有Lg / 5和Lg / 1之间的厚度。该结构使用最小或无晕轮植入物，以将沟道掺杂剂浓度维持在每立方厘米小于5×1017个掺杂剂原子。

公开(公告)号：US10217838B2

公开(公告)日：2019-02-26

申请号：US15963598

申请日：2018-04-26

申请人： Mie Fujitsu Semiconductor Limited

发明人： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/283

摘要： A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

公开(公告)号：US09991300B2

公开(公告)日：2018-06-05

申请号：US15658907

申请日：2017-07-25

申请人： Mie Fujitsu Semiconductor Limited

发明人： Teymur Bakhishev ,  Lingquan Wang ,  Dalong Zhao ,  Pushkar Ranade ,  Scott E. Thompson

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/146 ,  H04N5/3745 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/14616 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7833 ,  H01L29/7838 ,  H04N5/3745

摘要： Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

公开(公告)号：US09508728B2

公开(公告)日：2016-11-29

申请号：US15003151

申请日：2016-01-21

申请人： Mie Fujitsu Semiconductor Limited

发明人： Thomas Hoffmann ,  Pushkar Ranade ,  Scott E. Thompson

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC分类号： H01L27/1108 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966

摘要： A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.